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add SV VLIW idea
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 19 Jun 2019 15:03:32 +0000 (16:03 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 19 Jun 2019 15:03:32 +0000 (16:03 +0100)
simple_v_extension/specification.mdwn patch | blob | history

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index bbed3393126bf2bc9a24d5716d8fd2ee823a63b2..a6ea3e8744caba041d4f1d054a66c119d3c18032 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -2233,7 +2233,7 @@ Reminder of the variable-length format from Section 1.5 of the RISC-V ISA:
 | base+4 | base+2           | base             | number of bits             |
 | ------ | ---------------- | ---------------- | -------------------------- |
 | ..xxxx | xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 |
-| {ops}{Pred}{Reg}{VL}     || SV Prefix        |                            |
+|| {ops}{Pred}{Reg}{VL}     | SV Prefix        |                            |
 
 Notes:
 
http://libre-riscv.org ikiwiki