pysvp64asm: SVP64 instruction debug logs

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index b69448555a0fceabb2668f9b2bf81331cf1655ca..7f0b880cb616d7dd9853dde588590690789c4faa 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1462,6 +1462,8 @@ class SVP64Asm:
             if not v30b_op.endswith('.'):
                 v30b_op += rc
             yield "%s %s" % (v30b_op, ", ".join(v30b_newfields))
+        for (field, value, span) in svp64_insn.traverse("SVP64"):
+            log(field, f"{value.value:0{value.bits}b}", span)
         log("new v3.0B fields", v30b_op, v30b_newfields)
 
     def translate(self, lst):