* More complex HDL can be done by repeating existing scalar ALUs and pipelines as blocks.
* As (mostly) a high-level "context" that does not (significantly) deviate from scalar OpenPOWER ISA and, in its purest form being "a for loop around scalar instructions", it is minimally-disruptive and consequently stands a reasonable chance of broad community adoption and acceptance
* Completely wipes not just SIMD opcode proliferation off the
- map but off of Vectorisation ISAs as well. No more separate Vector
+ map (SIMD is O(N^6) opcode proliferation)
+ but off of Vectorisation ISAs as well. No more separate Vector
instructions.
Pages being developed and examples