More fixes in ternary op sign handling

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index a9574254dac33640301cfa0056587cbdf7d4706e..e7ceec5f9d277372cc38ef0765dece1d4c358ed1 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -998,6 +998,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
        // generate multiplexer for ternary operator (aka ?:-operator)
        case AST_TERNARY:
                {
+                       if (width_hint < 0)
+                               detectSignWidth(width_hint, sign_hint);
+
                        RTLIL::SigSpec cond = children[0]->genRTLIL();
                        RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
                        RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);

diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v
index c97a2be50b71c74b179fb32a969db4c16123d564..fffa3505081e8930224487731f5e8692a736d096 100644 (file)
--- a/tests/simple/vloghammer.v
+++ b/tests/simple/vloghammer.v
@@ -65,3 +65,11 @@ module test09(a, b, c, y);
   assign y = a ? b : c;
 endmodule
 
+module test10(a, b, c, y);
+  input a;
+  input signed [1:0] b;
+  input signed [2:0] c;
+  output y;
+  assign y = ^(a ? b : c);
+endmodule
+