simple_ram: Turn on pipelining

With a 1 cycle delay

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/simple_ram_behavioural.vhdl b/simple_ram_behavioural.vhdl
index 64135b81a830c20488a980b0549f14a6d6105518..d6255b8ed0e04440d99fdc268e48be6309270421 100644 (file)
--- a/simple_ram_behavioural.vhdl
+++ b/simple_ram_behavioural.vhdl
@@ -11,7 +11,7 @@ entity mw_soc_memory is
     generic (
         RAM_INIT_FILE  : string;
         MEMORY_SIZE    : integer;
-       PIPELINE_DEPTH : integer := 0
+       PIPELINE_DEPTH : integer := 1
         );
 
     port (