1999-12-30 Andrew Haley <aph@cygnus.com>

	* mips.h (OPCODE_IS_MEMBER): Add gp32 arg.

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 2be7ead39c68a5864478624b5779db76bc6c6e06..e8acc1c848f457fff95d75a1f302de671847bfa5 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+1999-12-30  Andrew Haley  <aph@cygnus.com>
+
+       * mips.h (OPCODE_IS_MEMBER): Add gp32 arg.
+
 2000-01-15  Alan Modra  <alan@spri.levels.unisa.edu.au>
 
        * i386.h: Qualify intel mode far call and jmp with x_Suf.

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 8c93d1bd7a3da131c0277d51a3667ea9e7eabc8b..3f9207ff3aa551efd2257d4c2bbe2e8bb87e0fb0 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -320,14 +320,18 @@ struct mips_opcode
 /* Toshiba R3900 instruction.  */
 #define INSN_3900                   0x00000080
 
+/* 32-bit code running on a ISA3+ CPU. */
+#define INSN_GP32                   0x00001000
+
 /* Test for membership in an ISA including chip specific ISAs.
    INSN is pointer to an element of the opcode table; ISA is the
    specified ISA to test against; and CPU is the CPU specific ISA
    to test, or zero if no CPU specific ISA test is desired. */ 
 
-#define OPCODE_IS_MEMBER(insn,isa,cpu)                                 \
+#define OPCODE_IS_MEMBER(insn,isa,cpu,gp32)                    \
     ((((insn)->membership & INSN_ISA) != 0                     \
-      && ((insn)->membership & INSN_ISA) <= isa)               \
+      && ((insn)->membership & INSN_ISA) <= isa                        \
+      && ((insn)->membership & INSN_GP32 ? gp32 : 1))          \
      || (cpu == 4650                                           \
         && ((insn)->membership & INSN_4650) != 0)              \
      || (cpu == 4010                                           \