reserve csr_map 0-->16 for gensoc internal csrs

diff --git a/targets/kc705.py b/targets/kc705.py
index 73505a852d2e0455e794bad1945a8f108d6c9cb2..6f278399a909554d0706835a9b57577ff1c20a2d 100644 (file)
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -66,8 +66,8 @@ class BaseSoC(SDRAMSoC):
        default_platform = "kc705"
 
        csr_map = {
-               "spiflash":     10,
-               "ddrphy":       11,
+               "spiflash":     16,
+               "ddrphy":       17,
        }
        csr_map.update(SDRAMSoC.csr_map)
 
@@ -110,8 +110,8 @@ class BaseSoC(SDRAMSoC):
 
 class MiniSoC(BaseSoC):
        csr_map = {
-               "ethphy":               12,
-               "ethmac":               13,
+               "ethphy":               18,
+               "ethmac":               19,
        }
        csr_map.update(BaseSoC.csr_map)
 

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index b30b86b2d1afc4f203678abda5a847f75e9ef695..dc4d58cb29437b9eddec7bdddbbdef820d3cf39c 100644 (file)
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -74,8 +74,8 @@ PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
 
 class MiniSoC(BaseSoC):
        csr_map = {
-               "ethphy":               10,
-               "ethmac":               11,
+               "ethphy":               16,
+               "ethmac":               17,
        }
        csr_map.update(BaseSoC.csr_map)
 
@@ -128,7 +128,7 @@ TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
 
 class FramebufferSoC(MiniSoC):
        csr_map = {
-               "fb":                                   12,
+               "fb":                                   18,
        }
        csr_map.update(MiniSoC.csr_map)
 

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index 069ff48e67ca4bee73d1183a91d36302f5e78f9a..4d7673ec2374990c9934ccbde886e885af2b24cd 100644 (file)
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
@@ -67,7 +67,7 @@ class BaseSoC(SDRAMSoC):
        default_platform = "pipistrello"
 
        csr_map = {
-               "spiflash":     10,
+               "spiflash":     16,
        }
        csr_map.update(SDRAMSoC.csr_map)
 

diff --git a/targets/ppro.py b/targets/ppro.py
index 761edcb88ebef197b82af2570b0c3885fc534fd3..a6f59d32c29890459ea2a32d203bef4d978b3e53 100644 (file)
--- a/targets/ppro.py
+++ b/targets/ppro.py
@@ -61,7 +61,7 @@ class BaseSoC(SDRAMSoC):
        default_platform = "papilio_pro"
 
        csr_map = {
-               "spiflash":     10,
+               "spiflash":     16,
        }
        csr_map.update(SDRAMSoC.csr_map)