(no commit message)

diff --git a/openpower/sv/fclass.mdwn b/openpower/sv/fclass.mdwn
index 64c432e9f3e2e22e02c316da0b8e5b7cbae528b0..6bc8f6263f12ce469ef0c43bbab3298ea4214f1d 100644 (file)
--- a/openpower/sv/fclass.mdwn
+++ b/openpower/sv/fclass.mdwn
@@ -1,8 +1,6 @@
 # fclass
 
-In SV just as with [[sv/fcvt]] single precision is to be considered half-of-elwidth precision.  Thus when elwidth=FP32 fptstsp will test half that precision, at FP16.
-
-based on xvtstdcsp v3.0B p768 the instruction performs analysis of the FP number to determine if it is Infinity, NaN, Denormalised or Zero and if so which sign.
+based on xvtstdcsp v3.0B p768 the instruction performs analysis of the FP number to determine if it is Infinity, NaN, Denormalised or Zero and if so which sign.  When VSX is not implemented these instructions become necessary.
 
 unlike xvtstdcsp the result is stored in a Condition Register
 Field specified by BF.
@@ -48,3 +46,6 @@ exponent <- src[1:11]
 fraction <- src[12:63]
       exponent & 7FF
 ```
+
+In SV just as with [[sv/fcvt]] single precision is to be considered half-of-elwidth precision.  Thus when elwidth=FP32 fptstsp will test half that precision, at FP16.
+