Add test

diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys
new file mode 100644 (file)
index 0000000..ee5c6bc
--- /dev/null
+++ b/tests/techmap/techmap_replace.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module sub(input i, output o, input j);
+foobar _TECHMAP_REPLACE_(i, o, j);
+wire _TECHMAP_REPLACE_.asdf = i ;
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+select -assert-any w:s0.asdf