bug 1236: add extra argument to svstep: RA.

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index 33a02e6612065f290d840e15a596dfc2177de5e5..3172bed40ffceea32220b40f3f0990a2845fa184 100644 (file)
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -5,8 +5,8 @@
 
 SVL-Form
 
-* svstep RT,SVi,vf (Rc=0)
-* svstep. RT,SVi,vf (Rc=1)
+* svstep RT,RA,SVi,vf (Rc=0)
+* svstep. RT,RA,SVi,vf (Rc=1)
 
 Pseudo-code:
 

diff --git a/openpower/isatables/RM-1P-1D.csv b/openpower/isatables/RM-1P-1D.csv
index c13f9a6f7382ef7c056bdbbf9760fd3be848da22..fc3978991b855201d3babccd531305f8860d2093 100644 (file)
--- a/openpower/isatables/RM-1P-1D.csv
+++ b/openpower/isatables/RM-1P-1D.csv
@@ -1,3 +1,2 @@
 insn,mode,CONDITIONS,Ptype,Etype,SM,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
 fmvis,NORMAL,,1P,EXTRA3,NO,d:FRS,0,0,0,0,0,0,FRS,0,0,0
-svstep,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,0,0,0,0,0,0,RT,0,CR0,0

diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv
index b24b4384ec77eb6af38c70bf44c4cb291be0214b..8216fdaa7ab6646fc86dd8d9d3258205880dfc8b 100644 (file)
--- a/openpower/isatables/RM-2P-1S1D.csv
+++ b/openpower/isatables/RM-2P-1S1D.csv
@@ -34,6 +34,7 @@ xori,NORMAL,,2P,EXTRA3,EN,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
 xoris,NORMAL,,2P,EXTRA3,EN,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
 subfic,NORMAL,,2P,EXTRA3,EN,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0
 fishmv,NORMAL,,2P,EXTRA3,EN,d:FRS,s:FRS,0,0,FRS,0,0,FRS,0,0,0
+svstep,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,CR0,0
 setvl,NORMAL,,2P,EXTRA3,EN,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT_OR_ZERO,0,CR0,0
 cntlzw,NORMAL,,2P,EXTRA3,EN,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
 cntlzd,NORMAL,,2P,EXTRA3,EN,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0

diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
index b8faabc3766f14035ef22efa5adf05e33dce06f0..f1342542425d65a75be988464211b2891bcf3d05 100644 (file)
--- a/openpower/isatables/minor_22.csv
+++ b/openpower/isatables/minor_22.csv
@@ -4,7 +4,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 -----11011-,VL,OP_SETVL,RA_OR_ZERO,NONE,NONE,RT_OR_ZERO,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,setvl,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 -----101001,VL,OP_SVINDEX,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svindex,SVI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 -----111001,VL,OP_SVREMAP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svremap,SVRM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
------10011-,VL,OP_SVSTEP,NONE,NONE,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,svstep,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----10011-,VL,OP_SVSTEP,RA_OR_ZERO,NONE,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,svstep,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 # svshape svshape2 fit same space, using 4-bits 21-24. svshape2 takes up two 4-bit patterns.
 # bit 25 is "vf" in svshape, and "sk" in svshape2 hence the "-" in between, in "NNNN-011001"
 0000-011001,VL,OP_SVSHAPE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svshape,SVM,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 9f362676b02230ee8feff334c2f0e5d9e83c9660..cc2c351eb361a19609e5cb654eaeff5358782158 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -3017,7 +3017,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
             self.svstate.vfirst = 0
         return nia_update
 
-    def SVSTATE_NEXT(self, mode, submode):
+    def SVSTATE_NEXT(self, mode, submode, RA=None):
         """explicitly moves srcstep/dststep on to next element, for
         "Vertical-First" mode.  this function is called from
         setvl pseudo-code, as a pseudo-op "svstep"

diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py
index a0661aa136d90bb354fc9adf5d15505ee06c8929..4d0336989fe2fd87d6e48c6f2c3fe99406e1572c 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_setvl.py
+++ b/src/openpower/decoder/isa/test_caller_setvl.py
@@ -296,8 +296,8 @@ class DecoderTestCase(FHDLTestCase):
 
     def test_svstep_1(self):
         lst = SVP64Asm(["setvl 0, 0, 10, 1, 1, 1",  # actual setvl (VF mode)
-                        "svstep 0, 1, 0",  # svstep
-                        "svstep 0, 1, 0",  # svstep
+                        "svstep 0, 0, 1, 0",  # svstep
+                        "svstep 0, 0, 1, 0",  # svstep
                         ])
         lst = list(lst)
 
@@ -327,8 +327,8 @@ class DecoderTestCase(FHDLTestCase):
         """tests svstep when it reaches VL
         """
         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",  # actual setvl (VF mode)
-                        "svstep. 0, 1, 0",  # svstep (Rc=1)
-                        "svstep. 0, 1, 0",  # svstep (Rc=1)
+                        "svstep. 0, 0, 1, 0",  # svstep (Rc=1)
+                        "svstep. 0, 0, 1, 0",  # svstep (Rc=1)
                         ])
         lst = list(lst)
 
@@ -365,8 +365,8 @@ class DecoderTestCase(FHDLTestCase):
         """tests svstep when it *doesn't* reach VL
         """
         lst = SVP64Asm(["setvl 0, 0, 3, 1, 1, 1",  # actual setvl (VF mode)
-                        "svstep. 0, 1, 0",  # svstep (Rc=1)
-                        "svstep. 0, 1, 0",  # svstep (Rc=1)
+                        "svstep. 0, 0, 1, 0",  # svstep (Rc=1)
+                        "svstep. 0, 0, 1, 0",  # svstep (Rc=1)
                         ])
         lst = list(lst)
 
@@ -580,12 +580,12 @@ class DecoderTestCase(FHDLTestCase):
             # set triple butterfly mode with persistent "REMAP"
             "svshape 8, 1, 1, 1, 1",
             "svremap 31, 1, 0, 2, 0, 1, 1",
-            "svstep. 0, 2, 0",  # svstep (Rc=1)
-            "svstep. 0, 2, 0",  # svstep (Rc=1)
-            "svstep. 0, 2, 0",  # svstep (Rc=1)
-            "svstep. 0, 2, 0",  # svstep (Rc=1)
-            "svstep. 0, 2, 0",  # svstep (Rc=1)
-            "svstep. 2, 2, 0",  # svstep (Rc=1)
+            "svstep. 0, 0, 2, 0",  # svstep (Rc=1)
+            "svstep. 0, 0, 2, 0",  # svstep (Rc=1)
+            "svstep. 0, 0, 2, 0",  # svstep (Rc=1)
+            "svstep. 0, 0, 2, 0",  # svstep (Rc=1)
+            "svstep. 0, 0, 2, 0",  # svstep (Rc=1)
+            "svstep. 2, 0, 2, 0",  # svstep (Rc=1)
         ])
         lst = list(lst)
 
@@ -624,9 +624,9 @@ class DecoderTestCase(FHDLTestCase):
             # set triple butterfly mode with persistent "REMAP"
             "svshape 8, 1, 1, 1, 1",
             "svremap 31, 1, 0, 2, 0, 1, 1",
-            "svstep. 0, 2, 0",  # svstep (Rc=1)
-            "svstep. 0, 2, 0",  # svstep (Rc=1)
-            "svstep. 0, 2, 0",  # svstep (Rc=1)
+            "svstep. 0, 0, 2, 0",  # svstep (Rc=1)
+            "svstep. 0, 0, 2, 0",  # svstep (Rc=1)
+            "svstep. 0, 0, 2, 0",  # svstep (Rc=1)
         ])
         lst = list(lst)
 
@@ -665,10 +665,10 @@ class DecoderTestCase(FHDLTestCase):
             # set triple butterfly mode with persistent "REMAP"
             "svshape 8, 1, 1, 1, 1",
             "svremap 31, 1, 0, 2, 0, 1, 1",
-            "svstep. 0, 2, 0",  # svstep (Rc=1)
-            "svstep. 0, 2, 0",  # svstep (Rc=1)
-            "svstep. 0, 2, 0",  # svstep (Rc=1)
-            "svstep. 0, 2, 0",  # svstep (Rc=1)
+            "svstep. 0, 0, 2, 0",  # svstep (Rc=1)
+            "svstep. 0, 0, 2, 0",  # svstep (Rc=1)
+            "svstep. 0, 0, 2, 0",  # svstep (Rc=1)
+            "svstep. 0, 0, 2, 0",  # svstep (Rc=1)
         ])
         lst = list(lst)
 
@@ -708,10 +708,10 @@ class DecoderTestCase(FHDLTestCase):
             # set triple butterfly mode with persistent "REMAP"
             "svshape 8, 1, 1, 1, 1",
             "svremap 31, 1, 0, 2, 0, 1, 1",
-            "svstep. 0, 2, 0",  # svstep (Rc=1)
-            "svstep. 0, 2, 0",  # svstep (Rc=1)
-            "svstep. 0, 2, 0",  # svstep (Rc=1)
-            "svstep. 2, 2, 0",  # svstep (Rc=1)
+            "svstep. 0, 0, 2, 0",  # svstep (Rc=1)
+            "svstep. 0, 0, 2, 0",  # svstep (Rc=1)
+            "svstep. 0, 0, 2, 0",  # svstep (Rc=1)
+            "svstep. 2, 0, 2, 0",  # svstep (Rc=1)
         ])
         lst = list(lst)
 
@@ -760,8 +760,8 @@ class DecoderTestCase(FHDLTestCase):
             # set FFT triple butterfly mode with persistent "REMAP"
             "svshape 8, 1, 1, 1, 0",
             "svremap 0, 0, 0, 2, 0, 1, 1",
-            "sv.svstep *0, 1, 1",  # svstep get vector of j+halfsize
-            "sv.svstep *16, 3, 1",  # svstep get vector of k in exptable[k]
+            "sv.svstep *0, 0, 1, 1",  # svstep get vector of j+halfsize
+            "sv.svstep *16, 0, 3, 1",  # svstep get vector of k in exptable[k]
         ])
         lst = list(lst)
 
@@ -828,10 +828,10 @@ class DecoderTestCase(FHDLTestCase):
         """tests svstep with an add, when it reaches VL
         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
                         'sv.add *1, *5, *9',
-                        "svstep. 0, 1, 0", # svstep (Rc=1)
+                        "svstep. 0, 0, 1, 0", # svstep (Rc=1)
                         "setvl. 0, 0, 1, 1, 0, 0",
                         'sv.add *1, *5, *9',
-                        "svstep. 3, 1, 0", # svstep (Rc=1)
+                        "svstep. 3, 0, 1, 0", # svstep (Rc=1)
                         "setvl 4, 0, 1, 0, 0, 0", # getvl
                         ])
         sequence is as follows:
@@ -846,9 +846,9 @@ class DecoderTestCase(FHDLTestCase):
         """
         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
                         'sv.add *1, *5, *9',
-                        "svstep. 0, 1, 0",  # svstep (Rc=1)
+                        "svstep. 0, 0, 1, 0",  # svstep (Rc=1)
                         'sv.add *1, *5, *9',
-                        "svstep. 3, 1, 0",  # svstep (Rc=1)
+                        "svstep. 3, 0, 1, 0",  # svstep (Rc=1)
                         "setvl 4, 0, 1, 0, 0, 0",  # getvl
                         ])
         lst = list(lst)
@@ -900,7 +900,7 @@ class DecoderTestCase(FHDLTestCase):
         """tests svstep with a branch.
         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
                         'sv.add *1, *5, *9',
-                        "svstep. 0, 1, 0", # svstep (Rc=1)
+                        "svstep. 0, 0, 1, 0", # svstep (Rc=1)
                         "bc 6, 3, -0xc"
                         ])
         sequence is as follows:
@@ -926,7 +926,7 @@ class DecoderTestCase(FHDLTestCase):
         """
         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
                         'sv.add *1, *5, *9',
-                        "svstep. 0, 1, 0",  # svstep (Rc=1)
+                        "svstep. 0, 0, 1, 0",  # svstep (Rc=1)
                         "bc 6, 3, -0xc"  # branch to add (64-bit op so -0xc!)
                         ])
         lst = list(lst)
@@ -981,9 +981,9 @@ class DecoderTestCase(FHDLTestCase):
         lst = SVP64Asm(["setvl 0, 0, 5, 1, 1, 1",
                         'sv.cmp 0, 1, *4, 14',  # r8 contains the temp
                         'sv.isel 14,*4,14,1',  # copy if cmp was greater
-                        "svstep. 12, 6, 0",  # get srcstep
+                        "svstep. 12, 0, 6, 0",  # get srcstep
                         'sv.isel 10,12,10,1',  # copy if cmp was greater
-                        "svstep. 0, 1, 0",  # svstep (Rc=1)
+                        "svstep. 0, 0, 1, 0",  # svstep (Rc=1)
                         "bc 6, 3, -0x24"  # branch to cmp
                         ])
         lst = list(lst)
@@ -1061,8 +1061,8 @@ class DecoderTestCase(FHDLTestCase):
         """tests svstep "straight", placing srcstep, dststep into vector
         """
         lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
-                        "sv.svstep *0, 5, 1",  # svstep get vector srcstep
-                        "sv.svstep. *4, 6, 1",  # svstep get vector dststep
+                        "sv.svstep *0, 0, 5, 1",  # svstep get vector srcstep
+                        "sv.svstep. *4, 0, 6, 1",  # svstep get vector dststep
                         ])
         lst = list(lst)
 
@@ -1100,8 +1100,8 @@ class DecoderTestCase(FHDLTestCase):
         """tests svstep "straight", placing srcstep, dststep into vector
         """
         lst = SVP64Asm(["setvl 0, 0, 5, 0, 1, 1",
-                        "sv.svstep/m=r30 *0, 5, 1",  # svstep get vector srcstep
-                        "sv.svstep./m=r30 *8, 6, 1", # svstep get vector dststep
+                        "sv.svstep/m=r30 *0,0,5,1",  # svstep get vector srcstep
+                        "sv.svstep./m=r30 *8,0,6,1", # svstep get vector dststep
                         ])
         lst = list(lst)
 

diff --git a/src/openpower/decoder/isa/test_caller_svp64_bc.py b/src/openpower/decoder/isa/test_caller_svp64_bc.py
index 36e4bd0bfc176fe310d409c159b7d8d7d767a635..25ade2f8de4ee3ede84dfe700e8a8808153cb95e 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_bc.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_bc.py
@@ -316,7 +316,7 @@ class DecoderTestCase(FHDLTestCase):
                 "setvl 0, 0, %d, 1, 1, 1" % maxvl, # VL = MAXVL = 2, vf=1
                 "sv.cmpi *cr0, 1, *10, 0x10", # compare reg val with immediate
                 "sv.bc 0, *2, 0x10", # jmp if CTR!=0 AND reg not equal to imm
-                "svstep. 27, 1, 0",
+                "svstep. 27, 0, 1, 0",
                 "bc 4, 3, -0x14", # CR_BI=0, jump to start of loop (sv.cmpi)
                 "or 0, 0, 0", # jump to here if terminate VF loop early
             ]

diff --git a/src/openpower/decoder/isa/test_caller_svp64_chacha20.py b/src/openpower/decoder/isa/test_caller_svp64_chacha20.py
index 01c5edbfaaaee5f12d2d5369689450b3d1ac87b8..1fd9a4d07e5f720ddb07a3d1a0d0483b958f0df3 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_chacha20.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_chacha20.py
@@ -162,8 +162,8 @@ class SVSTATETestCase(FHDLTestCase):
             'sv.xor/w=32 *%d, *%d, *%d' % (block, block, block),
             'svremap 31, 0, 3, 2, 2, 0, 0',  # RA=2, RB=3, RS=2 (0b01110)
             'sv.rldcl/w=32 *%d, *%d, *%d, 0' % (block, block, shifts),
-            'svstep. %d, 1, 0' % ctr,      # step to next in-regs element
-            'bc 6, 3, -0x28',               # svstep. Rc=1 loop-end-condition?
+            'svstep. %d, 0, 1, 0' % ctr,     # step to next in-regs element
+            'bc 6, 3, -0x28',                # svstep. Rc=1 loop-end-condition?
             # inner-loop done: outer loop standard CTR-decrement to setvl again
             'bc 16, 0, -0x30',
         ])

diff --git a/src/openpower/decoder/isa/test_caller_svp64_dct.py b/src/openpower/decoder/isa/test_caller_svp64_dct.py
index 581b35223e06ebc6d44e160bb1b7695536c367d0..96674d4a451c4046829bf0cb54a0044d06ea8668 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_dct.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_dct.py
@@ -438,8 +438,8 @@ class DCTTestCase(FHDLTestCase):
         """
         lst = SVP64Asm(["svshape 8, 1, 1, 5, 0",
                         "svremap 0, 0, 0, 2, 0, 1, 1",
-                        "sv.svstep *4, 3, 1",  # svstep get vector of ci
-                        "sv.svstep *16, 2, 1",  # svstep get vector of step
+                        "sv.svstep *4, 0, 3, 1",  # svstep get vector of ci
+                        "sv.svstep *16, 0, 2, 1",  # svstep get vector of step
                         "addi 1, 0, 0x0000",
                         "setvl 0, 0, 7, 0, 1, 1",
                         "sv.std *4, 0(1)",

diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py
index bc201c316fac0c6b0ed1ac8b9b28431f5f2d4b95..fdaefff08261c90ae9d85917ecb60fbcb7d67954 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_fft.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py
@@ -260,7 +260,7 @@ class FFTTestCase(FHDLTestCase):
                             "svshape 8, 1, 1, 1, 1",
                              "svremap 31, 1, 0, 2, 0, 1, 0",
                             "sv.ffmadds *0, *8, *0",
-                            "svstep. 12, 1, 0",
+                            "svstep. 12, 0, 1, 0",
                             "bc 6, 3, -16"
                             ])
             runs a full in-place O(N log2 N) butterfly schedule for
@@ -275,7 +275,7 @@ class FFTTestCase(FHDLTestCase):
             "svshape 8, 1, 1, 1, 1",
             "svremap 31, 1, 0, 2, 0, 1, 0",
             "sv.ffmadds *0, *8, *0",
-            "svstep. 27, 1, 0",
+            "svstep. 27, 0, 1, 0",
             "bc 6, 3, -16"
         ])
         lst = list(lst)
@@ -347,7 +347,7 @@ class FFTTestCase(FHDLTestCase):
                          # RA: scal RB: jl (S0) RC: n/a RT: jl (S0) EA: jh (S1)
                          "svremap 26, 0, 0, 0, 0, 1, 1",
                         "sv.ffadds *0, 24, *0",
-                        "svstep. 27, 1, 0",
+                        "svstep. 27, 0, 1, 0",
                         "bc 6, 3, -28"
                             ])
 
@@ -386,7 +386,7 @@ class FFTTestCase(FHDLTestCase):
             # RA: scal RB: jl (S0) RC: n/a RT: jl (S0) EA: jh (S1)
             "svremap 26, 0, 0, 0, 0, 1, 0",
             "sv.ffadds *0, 24, *0",
-            "svstep. 27, 1, 0",
+            "svstep. 27, 0, 1, 0",
             "bc 6, 3, -28"
         ])
         lst = list(lst)
@@ -622,7 +622,7 @@ class FFTTestCase(FHDLTestCase):
             "sv.ffadds *8, 26, *8",    # vh/vl +- tpim
 
             # svstep loop
-            "svstep. 27, 1, 0",
+            "svstep. 27, 0, 1, 0",
             "bc 6, 3, -56"
         ])
         lst = list(lst)

diff --git a/src/openpower/decoder/isa/test_caller_svp64_pack.py b/src/openpower/decoder/isa/test_caller_svp64_pack.py
index 0e83b9ebaf44f72ebd6755ecc63f28bb33f2b646..fb46a8b01efacc4b2c87dff2b5f26883c8e22d50 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_pack.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_pack.py
@@ -20,11 +20,11 @@ class DecoderTestCase(FHDLTestCase):
         """tests pack mode
         """
         lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
-                        "svstep 0, 15, 0",  # set dst-pack
-                        "sv.svstep./vec2 *0, 5, 1",  # svstep get vector srcstep
-                        "sv.svstep./vec2 *8, 6, 1",  # svstep get vector dststep
-                        "sv.svstep./vec2 *16, 7, 1",  # svstep get src substep
-                        "sv.svstep./vec2 *24, 8, 1",  # svstep get dst substep
+                        "svstep 0, 0, 15, 0",  # set dst-pack
+                        "sv.svstep./vec2 *0,0,5,1",  # svstep get vector srcstep
+                        "sv.svstep./vec2 *8,0,6,1",  # svstep get vector dststep
+                        "sv.svstep./vec2 *16,0,7,1",  # svstep get src substep
+                        "sv.svstep./vec2 *24,0,8,1",  # svstep get dst substep
                         ])
         lst = list(lst)
 
@@ -70,7 +70,7 @@ class DecoderTestCase(FHDLTestCase):
         the vector output in the order of their own values.
         """
         lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
-                        "svstep 0, 14, 0",  # set src-pack
+                        "svstep 0, 0, 14, 0",  # set src-pack
                         "sv.ori/vec2 *0, *32, 0",  # copy 01234567 to new order
                         ])
         lst = list(lst)
@@ -108,7 +108,7 @@ class DecoderTestCase(FHDLTestCase):
         """tests pack mode
         """
         lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
-                        "svstep 0, 15, 0",  # set dst-pack
+                        "svstep 0, 0, 15, 0",  # set dst-pack
                         "sv.ori/vec2 *0, *32, 0",  # copy 01234567 to new order
                         ])
         lst = list(lst)
@@ -146,7 +146,7 @@ class DecoderTestCase(FHDLTestCase):
         """tests pack mode with a predicate
         """
         lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
-                        "svstep 0, 15, 0",  # set dst-pack
+                        "svstep 0, 0, 15, 0",  # set dst-pack
                         "sv.ori/vec2/m=r3 *8, *16, 0",
                         ])
         lst = list(lst)
@@ -203,7 +203,7 @@ class DecoderTestCase(FHDLTestCase):
         """tests unpack mode with predicate
         """
         lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
-                        "svstep 0, 14, 0",  # set src-pack
+                        "svstep 0, 0, 14, 0",  # set src-pack
                         "sv.ori/vec2/m=r3 *8, *16, 0",  # copy with mask
                         ])
         lst = list(lst)

diff --git a/src/openpower/decoder/isa/test_caller_svstate.py b/src/openpower/decoder/isa/test_caller_svstate.py
index 48c4b6f24d87eed99520198ca60576b23e4997f7..88e77a7dc06814c848f01a49516710246f449de6 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svstate.py
+++ b/src/openpower/decoder/isa/test_caller_svstate.py
@@ -60,10 +60,10 @@ class SVSTATETestCase(FHDLTestCase):
         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
                         'sv.add 1, *5, *9',
                         'sv.addi *12, 1, 1',
-                        "svstep. 0, 1, 0",
+                        "svstep. 0, 0, 1, 0",
                         'sv.add 1, *5, *9',
                         'sv.addi *12, 1, 1',
-                        "svstep. 0, 1, 0",
+                        "svstep. 0, 0, 1, 0",
                         ])
 
         sequence is as follows:
@@ -92,10 +92,10 @@ class SVSTATETestCase(FHDLTestCase):
         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
                         'sv.add 1, *5, *9',       # scalar dest (into r1)
                         'sv.addi *12, 1, 1',       # scalar src (from r1)
-                        "svstep. 0, 1, 0",  # svstep
+                        "svstep. 0, 0, 1, 0",  # svstep
                         'sv.add 1, *5, *9',       # again, scalar dest
                         'sv.addi *12, 1, 1',       # but vector dest
-                        "svstep. 0, 1, 0",  # svstep (end: sets CR0.SO)
+                        "svstep. 0, 0, 1, 0",  # svstep (end: sets CR0.SO)
                         ])
         lst = list(lst)
 

diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py
index cc011e0a2d13ec302a28771d2167ee34f0585126..7db2ba86533a68f49152a4d63cbabf1eb2ae4812 100644 (file)
--- a/src/openpower/sv/sv_analysis.py
+++ b/src/openpower/sv/sv_analysis.py
@@ -539,8 +539,11 @@ def extra_classifier(insn_name, value, name, res, regs):
             res['0'] = 'd:FRS'  # FRS: Rdest1_EXTRA3
             res['1'] = 's:FRS'  # FRS: Rsrc1_EXTRA3
         elif insn_name == 'setvl':
-            res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
-            res['1'] = 's:RA'  # RS: Rsrc1_EXTRA3
+            res['0'] = 'd:RT'        # RT: Rdest1_EXTRA3
+            res['1'] = 's:RA'        # RS: Rsrc1_EXTRA3
+        elif insn_name == 'svstep':
+            res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA3
+            res['1'] = 's:RA'        # RA: Rsrc1_EXTRA3
         else:
             raise NotImplementedError(insn_name)
 
@@ -657,8 +660,6 @@ def extra_classifier(insn_name, value, name, res, regs):
 
     elif value == 'RM-1P-1D':
         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
-        if insn_name == 'svstep':
-            res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA3
         if insn_name == 'fmvis':
             res['0'] = 'd:FRS'  # FRS: Rdest1_EXTRA3