sim: bfin: handle saturation with RND12 sub insns

The current handling of the subtraction insn with the RND12 modifier
works when saturation isn't involved.  So add handling for this edge
case to match the hardware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog
index 008edf0f9d31cd268bde31cfcd36c471e41500c0..a28da1a3f6904781c88741e4263f2e79e2815de1 100644 (file)
--- a/sim/bfin/ChangeLog
+++ b/sim/bfin/ChangeLog
@@ -1,3 +1,8 @@
+2011-03-26  Robin Getz  <robin.getz@analog.com>
+
+       * bfin-sim.c (decode_dsp32alu_0): Set result to 0x7FFFFFFF when
+       the result was 0x80000000 for RND12 subtraction.
+
 2011-03-26  Robin Getz  <robin.getz@analog.com>
 
        * bfin-sim.c (decode_dsp32alu_0): Set VS when V is set.

diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c
index 7e747ff1e34ad0a4badfb34efeb1048d91174cc1..1555dc2c3f9493ab61c3d1e98b6583a26cdbf1b3 100644 (file)
--- a/sim/bfin/bfin-sim.c
+++ b/sim/bfin/bfin-sim.c
@@ -4009,7 +4009,12 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
 
       /* If subtract, just invert and add one.  */
       if (aop & 0x1)
-       val1 = ~val1 + 1;
+       {
+         if (val1 == 0x80000000)
+           val1 = 0x7FFFFFFF;
+         else
+           val1 = ~val1 + 1;
+       }
 
       /* Get the sign bits, since we need them later.  */
       sBit1 = !!(val0 & 0x80000000);