Test dffs separetely

diff --git a/tests/xilinx/dffs.v b/tests/xilinx/dffs.v
index d97840c439411c0c63b3df766a1798b5fc9caad8..3418787c9fbf25125d0e79cf11065d279df064a6 100644 (file)
--- a/tests/xilinx/dffs.v
+++ b/tests/xilinx/dffs.v
@@ -13,25 +13,3 @@ module dffe
                if ( en )
                        q <= d;
 endmodule
-
-module top (
-input clk,
-input en,
-input a,
-output b,b1,
-);
-
-dff u_dff (
-        .clk (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-dffe u_ndffe (
-        .clk (clk ),
-        .en (en),
-        .d (a ),
-        .q (b1 )
-    );
-
-endmodule

diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys
index 6a98994c02d6779df8a46f7dc5802e8948d8caff..2d48a816c0ffcbfd52c9888c756889f178b3e4aa 100644 (file)
--- a/tests/xilinx/dffs.ys
+++ b/tests/xilinx/dffs.ys
@@ -1,10 +1,25 @@
 read_verilog dffs.v
-hierarchy -top top
+design -save read
+
 proc
-flatten
+hierarchy -top dff
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
-select -assert-count 2 t:FDRE
+select -assert-count 1 t:FDRE
+
 select -assert-none t:BUFG t:FDRE %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top dffe
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDRE
+
+select -assert-none t:BUFG t:FDRE %% t:* %D
+