coolrunner2: Initial mapping of latches

diff --git a/techlibs/coolrunner2/Makefile.inc b/techlibs/coolrunner2/Makefile.inc
index d1672e782f050be8b54b33edcb116de2bbb992c4..96bbb0f4777bc71e2b79dfcb698e4079de8d9aa7 100644 (file)
--- a/techlibs/coolrunner2/Makefile.inc
+++ b/techlibs/coolrunner2/Makefile.inc
@@ -2,5 +2,6 @@
 OBJS += techlibs/coolrunner2/synth_coolrunner2.o
 OBJS += techlibs/coolrunner2/coolrunner2_sop.o
 
+$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_latch.v))
 $(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v))
 $(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/xc2_dff.lib))

diff --git a/techlibs/coolrunner2/cells_latch.v b/techlibs/coolrunner2/cells_latch.v
new file mode 100644 (file)
index 0000000..f1e19da
--- /dev/null
+++ b/techlibs/coolrunner2/cells_latch.v
@@ -0,0 +1,19 @@
+module $_DLATCH_P_(input E, input D, output Q);
+    LDCP _TECHMAP_REPLACE_ (
+        .D(D),
+        .G(E),
+        .Q(Q),
+        .PRE(1'b0),
+        .CLR(1'b0)
+        );
+endmodule
+
+module $_DLATCH_N_(input E, input D, output Q);
+    LDCP_N _TECHMAP_REPLACE_ (
+        .D(D),
+        .G(E),
+        .Q(Q),
+        .PRE(1'b0),
+        .CLR(1'b0)
+        );
+endmodule

diff --git a/techlibs/coolrunner2/cells_sim.v b/techlibs/coolrunner2/cells_sim.v
index f9f990c22f8deff095b22e72963ce3a2f674671f..90eb4eb16a980ebf390ddbdfbb6f3f0655309d40 100644 (file)
--- a/techlibs/coolrunner2/cells_sim.v
+++ b/techlibs/coolrunner2/cells_sim.v
@@ -94,3 +94,43 @@ module FDCP_N (C, PRE, CLR, D, Q);
             Q <= D;
     end
 endmodule
+
+module LDCP (G, PRE, CLR, D, Q);
+    parameter INIT = 0;
+
+    input G, PRE, CLR, D;
+    output reg Q;
+
+    initial begin
+        Q <= INIT;
+    end
+
+    always @* begin
+        if (CLR == 1)
+            Q <= 0;
+        else if (G == 1)
+            Q <= D;
+        else if (PRE == 1)
+            Q <= 1;
+    end
+endmodule
+
+module LDCP_N (G, PRE, CLR, D, Q);
+    parameter INIT = 0;
+
+    input G, PRE, CLR, D;
+    output reg Q;
+
+    initial begin
+        Q <= INIT;
+    end
+
+    always @* begin
+        if (CLR == 1)
+            Q <= 0;
+        else if (G == 0)
+            Q <= D;
+        else if (PRE == 1)
+            Q <= 1;
+    end
+endmodule

diff --git a/techlibs/coolrunner2/synth_coolrunner2.cpp b/techlibs/coolrunner2/synth_coolrunner2.cpp
index c58b52cdfc53f12f0576c4a09a2901e66dc7acc8..791bcffbeb6808533cec390476494b7c345432cd 100644 (file)
--- a/techlibs/coolrunner2/synth_coolrunner2.cpp
+++ b/techlibs/coolrunner2/synth_coolrunner2.cpp
@@ -145,6 +145,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
                {
                        run("opt -fast -full");
                        run("techmap");
+                       run("techmap -map +/coolrunner2/cells_latch.v");
                        run("dfflibmap -prepare -liberty +/coolrunner2/xc2_dff.lib");
                }
 
@@ -160,6 +161,8 @@ struct SynthCoolrunner2Pass : public ScriptPass
                        run("dfflibmap -liberty +/coolrunner2/xc2_dff.lib");
                        run("dffinit -ff FDCP Q INIT");
                        run("dffinit -ff FDCP_N Q INIT");
+                       run("dffinit -ff LDCP Q INIT");
+                       run("dffinit -ff LDCP_N Q INIT");
                        run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
                }