Add a name to timing_checker submodule

diff --git a/gram/phy/fakephy.py b/gram/phy/fakephy.py
index 16b5a4a5df770ca32b7747b1ecfea6738a517492..7da5447e2f9111b32d7c27daa100c4983a26c277 100644 (file)
--- a/gram/phy/fakephy.py
+++ b/gram/phy/fakephy.py
@@ -542,7 +542,7 @@ class FakePHY(Elaboratable):
                 refresh_mode = self.module.timing_settings.fine_refresh_mode,
                 memtype      = self.settings.memtype,
                 verbose      = self.verbosity > SDRAM_VERBOSE_DBG)
-            m.submodules += timing_checker
+            m.submodules.timing_checker = timing_checker
 
         # Bank init data ---------------------------------------------------------------------------
         bank_init  = [None for i in range(nbanks)]