+2016-06-29 Richard Biener <rguenther@suse.de>
+
+ PR rtl-optimization/68961
+ * simplify-rtx.c (simplify_subreg): Handle VEC_CONCAT like CONCAT.
+
2016-06-29 Richard Biener <rguenther@suse.de>
PR middle-end/71002
&& GET_MODE_SIZE (outermode) <= GET_MODE_SIZE (GET_MODE (op)))
return adjust_address_nv (op, outermode, byte);
- /* Handle complex values represented as CONCAT
- of real and imaginary part. */
- if (GET_CODE (op) == CONCAT)
+ /* Handle complex or vector values represented as CONCAT or VEC_CONCAT
+ of two parts. */
+ if (GET_CODE (op) == CONCAT
+ || GET_CODE (op) == VEC_CONCAT)
{
unsigned int part_size, final_offset;
rtx part, res;
if (final_offset + GET_MODE_SIZE (outermode) > part_size)
return NULL_RTX;
- res = simplify_subreg (outermode, part, GET_MODE (part), final_offset);
+ enum machine_mode part_mode = GET_MODE (part);
+ if (part_mode == VOIDmode)
+ part_mode = GET_MODE_INNER (GET_MODE (op));
+ res = simplify_subreg (outermode, part, part_mode, final_offset);
if (res)
return res;
- if (validate_subreg (outermode, GET_MODE (part), part, final_offset))
+ if (validate_subreg (outermode, part_mode, part, final_offset))
return gen_rtx_SUBREG (outermode, part, final_offset);
return NULL_RTX;
}