r100: fixup radeon so gears seems to work

diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile
index 2ef3640e1d0cacb64991c29ab805ca9afa3f5e9c..2d00f521a608972fa3ff31a21f4ce62f5ffa3137 100644 (file)
--- a/src/mesa/drivers/dri/radeon/Makefile
+++ b/src/mesa/drivers/dri/radeon/Makefile
@@ -24,7 +24,8 @@ DRIVER_SOURCES = \
        common_lock.c \
        common_misc.c \
        radeon_bo_legacy.c \
-       radeon_cs_legacy.c
+       radeon_cs_legacy.c \
+       radeon_mipmap_tree.c
 
 C_SOURCES = \
        $(COMMON_SOURCES) \

diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c
index ec5300712229d1d13e35ca8f9a5e10faa5e75e74..fbabed19f196ecb4aa4f3b0463fd39844d750b75 100644 (file)
--- a/src/mesa/drivers/dri/radeon/common_misc.c
+++ b/src/mesa/drivers/dri/radeon/common_misc.c
@@ -752,12 +752,12 @@ static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name)
                        radeon->radeonScreen->AGPMode;
                const char* chipname;
 
-                       
-
                if (IS_R300_CLASS(radeon->radeonScreen))
                        chipname = "R300";
-               else
+               else if (IS_R200_CLASS(radeon->radeonScreen))
                        chipname = "R200";
+               else
+                       chipname = "R100";
 
                offset = driGetRendererString(buffer, chipname, DRIVER_DATE,
                                              agp_mode);

diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c
index aa1cd5e300d4f66072449ab3fcb4a79330a755c4..1d756bd868b541d2dde288c9a796af4040aadd16 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -235,6 +235,12 @@ static void r100_vtbl_emit_state(radeonContextPtr rmesa)
        radeonEmitState((r100ContextPtr)rmesa);
 }
 
+static void r100_vtbl_flush_vertices(radeonContextPtr rmesa)
+{
+  RADEON_FIREVERTICES(((r100ContextPtr)rmesa));
+}
+
+
 static void r100_init_vtbl(radeonContextPtr radeon)
 {
    radeon->vtbl.get_lock = r100_get_lock;
@@ -245,6 +251,7 @@ static void r100_init_vtbl(radeonContextPtr radeon)
    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
    radeon->vtbl.emit_state = r100_vtbl_emit_state;
    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
+   radeon->vtbl.flush_vertices = r100_vtbl_flush_vertices;
 }
 
 /* Create the device specific context.
@@ -258,7 +265,7 @@ radeonCreateContext( const __GLcontextModes *glVisual,
    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
    struct dd_function_table functions;
    r100ContextPtr rmesa;
-   GLcontext *ctx, *shareCtx;
+   GLcontext *ctx;
    int i;
    int tcl_mode, fthrottle_mode;
 
@@ -313,6 +320,7 @@ radeonCreateContext( const __GLcontextModes *glVisual,
    (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) );
    make_empty_list( & rmesa->radeon.swapped );
 
+#if 0
    rmesa->radeon.nr_heaps = screen->numTexHeaps;
    for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
       rmesa->radeon.texture_heaps[i] = driCreateTextureHeap( i, rmesa,
@@ -328,6 +336,7 @@ radeonCreateContext( const __GLcontextModes *glVisual,
       driSetTextureSwapCounterLocation( rmesa->radeon.texture_heaps[i],
                                        & rmesa->c_textureSwaps );
    }
+#endif
    rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache,
                                           "texture_depth");
    if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)

diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index 94e930a1f440c8f38f386f36791c858266a69cd1..4ab297c5ceebf195041361ab9203ce006493c9f4 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -59,19 +59,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define RADEON_TIMEOUT             512
 #define RADEON_IDLE_RETRY           16
 
-
-
-static void print_state_atom( struct radeon_state_atom *state )
-{
-   int i;
-
-   fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size);
-
-   if (RADEON_DEBUG & DEBUG_VERBOSE) 
-      for (i = 0 ; i < state->cmd_size ; i++) 
-        fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]);
-
-}
+#define DEBUG_CMDBUF         0
 
 static void radeonSaveHwState( r100ContextPtr rmesa )
 {
@@ -90,7 +78,7 @@ static void radeonSaveHwState( r100ContextPtr rmesa )
         dest += size;
         rmesa->backup_store.cmd_used += size;
         if (RADEON_DEBUG & DEBUG_STATE)
-           print_state_atom( atom );
+           radeon_print_state_atom( atom );
       }
    }
 
@@ -166,6 +154,40 @@ void radeonSetUpAtomList( r100ContextPtr rmesa )
    insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.glt);
 }
 
+static INLINE void radeonEmitAtoms(r100ContextPtr r100, GLboolean dirty)
+{
+   BATCH_LOCALS(&r100->radeon);
+   struct radeon_state_atom *atom;
+   int dwords;
+
+   /* Emit actual atoms */
+   foreach(atom, &r100->hw.atomlist) {
+     if ((atom->dirty || r100->hw.all_dirty) == dirty) {
+       dwords = (*atom->check) (r100->radeon.glCtx, atom);
+       if (dwords) {
+         if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
+            radeon_print_state_atom(atom);
+         }
+        if (atom->emit) {
+          (*atom->emit)(r100->radeon.glCtx, atom);
+        } else {
+          BEGIN_BATCH_NO_AUTOSTATE(dwords);
+          OUT_BATCH_TABLE(atom->cmd, dwords);
+          END_BATCH();
+        }
+        atom->dirty = GL_FALSE;
+       } else {
+         if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
+            fprintf(stderr, "  skip state %s\n",
+                    atom->name);
+         }
+       }
+     }
+   }
+   
+   COMMIT_BATCH();
+}
+
 void radeonEmitState( r100ContextPtr rmesa )
 {
    struct radeon_state_atom *atom;
@@ -180,6 +202,9 @@ void radeonEmitState( r100ContextPtr rmesa )
       rmesa->save_on_next_emit = GL_FALSE;
    }
 
+   if (rmesa->radeon.cmdbuf.cs->cdw)
+       return;
+
    /* this code used to return here but now it emits zbs */
 
    /* To avoid going across the entire set of states multiple times, just check
@@ -195,44 +220,20 @@ void radeonEmitState( r100ContextPtr rmesa )
       you get tcl lockups on at least M7/7500 class of chips - airlied */
    rmesa->hw.zbs.dirty=1;
 
-   if (RADEON_DEBUG & DEBUG_STATE) {
-      foreach(atom, &rmesa->hw.atomlist) {
-        if (atom->dirty || rmesa->hw.all_dirty) {
-           if (atom->check(rmesa->radeon.glCtx, 0))
-              print_state_atom(atom);
-           else
-              fprintf(stderr, "skip state %s\n", atom->name);
-        }
-      }
+   if (!rmesa->radeon.cmdbuf.cs->cdw) {
+     if (RADEON_DEBUG & DEBUG_STATE)
+       fprintf(stderr, "Begin reemit state\n");
+     
+     radeonEmitAtoms(rmesa, GL_FALSE);
    }
 
-   foreach(atom, &rmesa->hw.atomlist) {
-      if (rmesa->hw.all_dirty)
-        atom->dirty = GL_TRUE;
-      if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) &&
-          atom->is_tcl)
-        atom->dirty = GL_FALSE;
-      if (atom->dirty) {
-       dwords = atom->check(rmesa->radeon.glCtx, atom);
-       if (dwords) {
-           int size = atom->cmd_size * 4;
-           
-           if (atom->emit) {
-             (*atom->emit)(rmesa->radeon.glCtx, atom);
-           } else {
-             memcpy(dest, atom->cmd, size);
-             dest += size;
-             rmesa->store.cmd_used += size;
-           }
-           atom->dirty = GL_FALSE;
-        }
-      }
-   }
+   if (RADEON_DEBUG & DEBUG_STATE)
+     fprintf(stderr, "Begin dirty state\n");
 
-   assert(rmesa->store.cmd_used <= RADEON_CMD_BUF_SZ);
- 
+   radeonEmitAtoms(rmesa, GL_TRUE);
    rmesa->hw.is_dirty = GL_FALSE;
    rmesa->hw.all_dirty = GL_FALSE;
+
 }
 
 /* Fire a section of the retained (indexed_verts) buffer as a regular
@@ -422,7 +423,7 @@ void radeonEmitAOS( r100ContextPtr rmesa,
 }
 
 
-
+#if 0
 /* using already shifted color_fmt! */
 void radeonEmitBlit( r100ContextPtr rmesa, /* FIXME: which drmMinor is required? */
                   GLuint color_fmt,
@@ -487,6 +488,7 @@ void radeonEmitWait( r100ContextPtr rmesa, GLuint flags )
    cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
    cmd[0].wait.flags = flags;
 }
+#endif
 
 /* ================================================================
  * Buffer clear
@@ -681,12 +683,12 @@ void radeonFlush( GLcontext *ctx )
       fprintf(stderr, "%s\n", __FUNCTION__);
 
    if (rmesa->radeon.dma.flush)
-      rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
+      rmesa->radeon.dma.flush( ctx );
 
    radeonEmitState( rmesa );
    
-   if (rmesa->store.cmd_used)
-      radeonFlushCmdBuf( rmesa, __FUNCTION__ );
+   if (rmesa->radeon.cmdbuf.cs->cdw)
+      rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
 }
 
 /* Make sure all commands have been sent to the hardware and have

diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c
index 0c9fb14857c10d8100c785d2680774bd8a3f2619..1d683e5b3aae5892a4c27c38d52f1956cc71a634 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_state.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state.c
@@ -2091,34 +2091,23 @@ radeonUpdateDrawBuffer(GLcontext *ctx)
 {
    r100ContextPtr rmesa = R100_CONTEXT(ctx);
    struct gl_framebuffer *fb = ctx->DrawBuffer;
-   driRenderbuffer *drb;
+   struct radeon_renderbuffer *rrb;
 
    if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) {
-      /* draw to front */
-      drb = (driRenderbuffer *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
-   }
-   else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
-      /* draw to back */
-      drb = (driRenderbuffer *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
-   }
-   else {
-      /* drawing to multiple buffers, or none */
-      return;
+     /* draw to front */
+     rrb = (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+   } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
+     /* draw to back */
+     rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+   } else {
+     /* drawing to multiple buffers, or none */
+     return;
    }
 
-   assert(drb);
-   assert(drb->flippedPitch);
+   assert(rrb);
+   assert(rrb->pitch);
 
    RADEON_STATECHANGE( rmesa, ctx );
-
-   /* Note: we used the (possibly) page-flipped values */
-   rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET]
-     = ((drb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation)
-       & RADEON_COLOROFFSET_MASK);
-   rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch;
-   if (rmesa->radeon.sarea->tiling_enabled) {
-      rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
-   }
 }
 
 

diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index f39fae8186cbbba3b5f2dc140edce3e22e000e74..02ea616a59e8ee5ea445282d813d1d46d588e361 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -614,4 +614,6 @@ void radeonInitState( r100ContextPtr rmesa )
    rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
    
    rmesa->hw.all_dirty = GL_TRUE;
+
+   rcommonInitCmdBuf(&rmesa->radeon, rmesa->hw.max_state_size);
 }