rst : Signal or None, inout
Reset signal for this domain. Can be driven or used to drive.
"""
+
+ @staticmethod
+ def _name_for(domain_name, signal_name):
+ if domain_name == "sync":
+ return signal_name
+ else:
+ return "{}_{}".format(domain_name, signal_name)
+
def __init__(self, name=None, reset_less=False, async_reset=False):
if name is None:
try:
name = name[3:]
self.name = name
- self.clk = Signal(name=self.name + "_clk", src_loc_at=1)
+ self.clk = Signal(name=self._name_for(name, "clk"), src_loc_at=1)
if reset_less:
self.rst = None
else:
- self.rst = Signal(name=self.name + "_rst", src_loc_at=1)
+ self.rst = Signal(name=self._name_for(name, "rst"), src_loc_at=1)
self.async_reset = async_reset
+
+ def rename(self, name):
+ self.name = name
+ self.clk.name = self._name_for(name, "clk")
+ if self.rst is not None:
+ self.rst.name = self._name_for(name, "rst")
if domain in self.domain_map:
if cd.name == domain:
# Rename the actual ClockDomain object.
- cd.name = self.domain_map[domain]
+ cd.rename(self.domain_map[domain])
else:
assert cd.name == self.domain_map[domain]
new_fragment.add_domains(cd)
class ClockDomainCase(FHDLTestCase):
def test_name(self):
+ sync = ClockDomain()
+ self.assertEqual(sync.name, "sync")
+ self.assertEqual(sync.clk.name, "clk")
+ self.assertEqual(sync.rst.name, "rst")
pix = ClockDomain()
self.assertEqual(pix.name, "pix")
+ self.assertEqual(pix.clk.name, "pix_clk")
+ self.assertEqual(pix.rst.name, "pix_rst")
cd_pix = ClockDomain()
self.assertEqual(pix.name, "pix")
dom = [ClockDomain("foo")][0]
self.assertIsNotNone(pix.clk)
self.assertIsNotNone(pix.rst)
self.assertTrue(pix.async_reset)
+
+ def test_rename(self):
+ sync = ClockDomain()
+ self.assertEqual(sync.name, "sync")
+ self.assertEqual(sync.clk.name, "clk")
+ self.assertEqual(sync.rst.name, "rst")
+ sync.rename("pix")
+ self.assertEqual(sync.name, "pix")
+ self.assertEqual(sync.clk.name, "pix_clk")
+ self.assertEqual(sync.rst.name, "pix_rst")