DMAWriteController: fix Demultiplexer layout

diff --git a/migen/actorlib/spi.py b/migen/actorlib/spi.py
index eff515e67f64b78466cb0fc0c3198fd32206036f..7146796bf50e5ba46a5ddde0bb32208c96018c67 100644 (file)
--- a/migen/actorlib/spi.py
+++ b/migen/actorlib/spi.py
@@ -163,7 +163,7 @@ class DMAWriteController(_DMAController):
                self.submodules += comp_actor
 
                if ack_when_inactive:
-                       demultiplexer = plumbing.Demultiplexer(comp_actor.d.payload.layout, 2)
+                       demultiplexer = plumbing.Demultiplexer([("d", bus_dw)], 2)
                        self.comb +=[
                                demultiplexer.sel.eq(~adr_buffer.busy),
                                demultiplexer.source0.connect(comp_actor.d),