+2012-12-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/arm/arm.md (f_minmaxs, f_minmaxd): New types.
+ * config/arm/vfp.md (smax<mode>3): New pattern.
+ (smin<mode>3): Likewise.
+
2012-12-19 Richard Biener <rguenther@suse.de>
* targhooks.h (default_canonicalize_comparison): Fix prototype.
fmacd,\
f_rints,\
f_rintd,\
+ f_minmaxs,\
+ f_minmaxd,\
f_flag,\
f_loads,\
f_loadd,\
(set_attr "type" "f_rint<vfp_type>")]
)
+;; MIN_EXPR and MAX_EXPR eventually map to 'smin' and 'smax' in RTL.
+;; The 'smax' and 'smin' RTL standard pattern names do not specify which
+;; operand will be returned when both operands are zero (i.e. they may not
+;; honour signed zeroes), or when either operand is NaN. Therefore GCC
+;; only introduces MIN_EXPR/MAX_EXPR in fast math mode or when not honouring
+;; NaNs.
+
+(define_insn "smax<mode>3"
+ [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+ (smax:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
+ (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
+ "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
+ "vmaxnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+ [(set_attr "type" "f_minmax<vfp_type>")]
+)
+
+(define_insn "smin<mode>3"
+ [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+ (smin:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
+ (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
+ "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
+ "vminnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+ [(set_attr "type" "f_minmax<vfp_type>")]
+)
+
;; Unimplemented insns:
;; fldm*
;; fstm*
+2012-12-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * gcc.target/arm/vmaxnmdf.c: New test.
+ * gcc.target/arm/vmaxnmsf.c: Likewise.
+ * gcc.target/arm/vminnmsf.c: Likewise.
+ * gcc.target/arm/vminnmdf.c: Likewise.
+
2012-12-19 Tobias Burnus <burnus@net-b.de>
* gfortran.dg/gomp/use_intrinsic_1.f90: Moved
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-ffast-math" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x, double y)
+{
+ return __builtin_fmax (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+" 1 } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-ffast-math" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x, float y)
+{
+ return __builtin_fmaxf (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vmaxnm.f32\ts\[0-9\]+" 1 } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-ffast-math" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x, double y)
+{
+ return __builtin_fmin (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+" 1 } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-ffast-math" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x, float y)
+{
+ return __builtin_fminf (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vminnm.f32\ts\[0-9\]+" 1 } } */