* config/tc-z80.c (z80_start_line_hook): issue an error when
redefining a symbol with equ
- * doc/as.texinfo(equ<z80>): mention difference with .equiv
- * doc/as.texinfo(err): fix typo
- * doc/c-z80.texi(equ): redefining a symbol with equ is no longer
+ * doc/as.texinfo(equ<z80>): mention difference with .equiv
+ * doc/as.texinfo(err): fix typo
+ * doc/c-z80.texi(equ): redefining a symbol with equ is no longer
allowed
2005-11-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
Delete the code handling large constant for PIC.
Modify some comments.
(score_relax_frag): Decrease insn_addr in certain situation.
- (s_score_cprestore): Change .cprestore syntax from ".cprestore offset"
+ (s_score_cprestore): Change .cprestore syntax from ".cprestore offset"
to ".cprestore reg, offset".
-
+
2006-12-23 Kazu Hirata <kazu@codesourcery.com>
* configure.tgt: Recognize fido.
* config/tc-mips.c (mips_ip) <'('>: Don't let '4', '5' or '-'
as a base register specifier.
-
+
2010-12-09 Maciej W. Rozycki <macro@codesourcery.com>
* config/tc-mips.c (macro) <M_S_DOB>: Fix the placement of code.
(fixup_segment): Use MD_PCREL_FROM_SECTION instead of
md_pcrel_from, and TC_FORCE_RELOCATION_SECTION instead of
TC_FORCE_RELOCATION.
-
+
Mon Oct 23 16:20:04 1995 Ken Raeburn <raeburn@cygnus.com>
* input-scrub.c (as_where): Set name to null pointer if we don't
accepting the 4100 as a MIPS architecture variant (md_begin,
macro_build, mips_ip, md_parse_option). Adding suitable
command-line OPTIONs, and updating the help text (md_show_usage).
-
+
Wed Oct 18 13:20:32 1995 Ken Raeburn <raeburn@cygnus.com>
* subsegs.c (subseg_begin): Only set absolute_frchain.fix_* when
Thu Sep 28 15:43:15 1995 Kim Knuttila <krk@nellie>
- * config/tc-ppc.c (md_apply_fix3): Removed some TE_PE specific
+ * config/tc-ppc.c (md_apply_fix3): Removed some TE_PE specific
manipulations, since I can't prove they're needed.
(md_begin): Removed init_regtable, insert_reg, and the call points.
(register_name): New function. Parses a register name, if appropriate.
Added support for more predefined sections
(ppc_frob_section): Removed some xcoff specific processing from TE_PE
(ppc_fix_adjustable): Removed from TE_PE mainline
- (md_apply_fix3): For TE_PE toc entries, we don't need to mess
+ (md_apply_fix3): For TE_PE toc entries, we don't need to mess
with fx_addnumber. Removed for the time being.
(lots): Put back missing assignments to ppc_current_csect.
(md_assemble): Be more robust in terms of relocations.
(md_apply_fix3): Allow 14 bit relocs to be emitted for external
symbols in addition to 26 bit relocs. Properly insert 26/14 bit
- reloc value fields into the instruction stream.
+ reloc value fields into the instruction stream.
Mon Sep 25 00:23:16 1995 Ian Lance Taylor <ian@cygnus.com>
(build_Mytes, md_atof): Likewise.
(md_convert_frag, md_apply_fix): Likewise.
(md_number_to_chars): Likewise.
-
+
Wed Aug 9 10:51:48 1995 Ian Lance Taylor <ian@cygnus.com>
* config/tc-m68k.c (m68k_abspcadd): New static variable.
* gasp.c (main): Parse -I option.
(do_include): Look through include list.
- * gasp.c (change_base): Don't modify numbers in strings.
+ * gasp.c (change_base): Don't modify numbers in strings.
Mon Jul 31 12:16:21 1995 Ian Lance Taylor <ian@cygnus.com>
Add SPARC ELF PIC support.
* write.c (fixup_segment): Pass fixP to TC_RELOC_RTSYM_LOC_FIXUP,
not fixP->fx_r_type.
- * config/tc-sparc.c (sparc_pic_code): New global variable.
+ * config/tc-sparc.c (sparc_pic_code): New global variable.
(md_apply_fix): If generating PIC, adjust fx_addnumber for any non
PC relative reloc.
(tc_gen_reloc): If generating PIC, adjust various reloc types.
(s_stringer, s_mips_space): Remove unneeded declarations.
(md_parse_option): In case 'g', set mips_debug to debugging level.
(mips_local_label): New function.
- * config/tc-mips.h (LOCAL_LABEL): Call mips_local_label.
+ * config/tc-mips.h (LOCAL_LABEL): Call mips_local_label.
(mips_local_label): Declare.
Wed Jul 5 00:59:22 1995 Fred Fish (fnf@cygnus.com)
* config/atof-ieee.c, config/atof-ns32k.c, config/tc-*.c: made
EXP_CHARS, FLT_CHARS, comment_chars, line_comment_chars and
line_seperator_chars consistently const, and always
- initialized them. Included read.h.
+ initialized them. Included read.h.
Thu Nov 5 17:55:41 1992 Jim Wilson (wilson@sphagnum.cygnus.com)
* config/tc-i960.h, config/tc-i960.c: avoid the ANSI
preprocessor addition #elif, since it is not supported by old
- compilers.
+ compilers.
config/ho-rs6000.h, config/tc-m68k.c: the native RS/6000
compiler miscompiles a couple of expressions in tc-m68k.c.
file.
* config/tc-m68kmote.c, config/tc-m68kmote.h: removed now
superfluous files.
-
+
From Steve Chamberlain:
* config/m68kcoff.mt: for m68k COFF.
* config/obj-coffbfd.c: (fixup_mdeps) added
`sparc-sun-sunos4'.
The `configure' script accompanying GAS does not provide any query
-facility to list all supported host and target names or aliases.
+facility to list all supported host and target names or aliases.
`configure' calls the Bourne shell script `config.sub' to map
abbreviations to full names; you can read the script, if you wish, or
you can use it to test your guesses on abbreviations--for example:
targets.
`--enable-OPTION'
- These flags tell the program or library being configured to
+ These flags tell the program or library being configured to
configure itself differently from the default for the specified
host/target combination. See below for a list of `--enable'
options recognized in the gas distribution.
/* This is a utility function called from various tc-*.c files. It
is here in order to reduce code duplication.
-
+
Turn a string at input_line_pointer into a floating point constant
of type TYPE (a character found in the FLT_CHARS macro), and store
it as LITTLENUMS in the bytes buffer LITP. The number of chars
Address of where to build floating point literal.
Assumed to be 'big enough'.
Address of where to return size of literal (in chars).
-
+
Out: Input_line_pointer->of next char after floating number.
Error message, or 0.
Floating point literal.
#define yylval m68k_lval
#define yychar m68k_char
#define yydebug m68k_debug
-#define yypact m68k_pact
-#define yyr1 m68k_r1
-#define yyr2 m68k_r2
-#define yydef m68k_def
-#define yychk m68k_chk
-#define yypgo m68k_pgo
-#define yyact m68k_act
+#define yypact m68k_pact
+#define yyr1 m68k_r1
+#define yyr2 m68k_r2
+#define yydef m68k_def
+#define yychk m68k_chk
+#define yypgo m68k_pgo
+#define yyact m68k_act
#define yyexca m68k_exca
#define yyerrflag m68k_errflag
#define yynerrs m68k_nerrs
{
yylval.exp.pic_reloc = pic_tls_ie;
tail += 6;
- }
+ }
else if (strncmp (cp - 6, "@TLSLE", 6) == 0)
{
yylval.exp.pic_reloc = pic_tls_le;
tail += 6;
- }
+ }
}
else if (cp - 4 > str && cp[-4] == '@')
{
#define SF_IS_SYSPROC 0x00000040 /* bit 6 marks symbols that are sysprocs. */
#define SF_BALNAME 0x00000080 /* bit 7 marks BALNAME symbols. */
#define SF_CALLNAME 0x00000100 /* bit 8 marks CALLNAME symbols. */
-
+
#define SF_NORMAL_MASK 0x0000ffff /* bits 12-15 are general purpose. */
-
+
#define SF_STATICS 0x00001000 /* Mark the .text & all symbols. */
#define SF_DEFINED 0x00002000 /* Symbol is defined in this file. */
#define SF_STRING 0x00004000 /* Symbol name length > 8. */
#define SF_LOCAL 0x00008000 /* Symbol must not be emitted. */
-
+
#define SF_DEBUG_MASK 0xffff0000 /* bits 16-31 are debug info. */
-
+
#define SF_FUNCTION 0x00010000 /* The symbol is a function. */
#define SF_PROCESS 0x00020000 /* Process symbol before write. */
#define SF_TAGGED 0x00040000 /* Is associated with a tag. */
list.elt_count = NULL;
list.indexes = hash_new ();
bfd_map_over_sections (stdoutput, build_group_lists, &list);
-
+
/* Make the SHT_GROUP sections that describe each section group. We
can't set up the section contents here yet, because elf section
indices have yet to be calculated. elf.c:set_group_contents does
which further designates that the name was truncated):
"original_identifier"_haaaaabbbccc
-
+
aaaaa = 32-bit CRC
bbb = length of original identifier
ccc = sum of 32-bit CRC characters
/* Table used by the crc32 function to calcuate the checksum. */
static unsigned int crc32_table[256] = {0, 0};
-/* Given a string in BUF, calculate a 32-bit CRC for it.
+/* Given a string in BUF, calculate a 32-bit CRC for it.
This is used as a reasonably unique hash for the given string. */
a truncated identifier. */
if (len != MAX_LABEL_LENGTH)
return 0;
-
+
/* Start scanning backwards for a _h. */
len = len - 3 - 3 - 5 - 2;
ptr = id + len;
decorations. */
/* Mach-O supports multiple, named segments each of which may contain
- multiple named sections. Thus the concept of subsectioning is
+ multiple named sections. Thus the concept of subsectioning is
handled by (say) having a __TEXT segment with appropriate flags from
- which subsections are generated like __text, __const etc.
-
+ which subsections are generated like __text, __const etc.
+
The well-known as short-hand section switch directives like .text, .data
etc. are mapped onto predefined segment/section pairs using facilites
supplied by the mach-o port of bfd.
-
+
A number of additional mach-o short-hand section switch directives are
also defined. */
subseg_set (text_section, 0);
if (obj_mach_o_is_static)
{
- bfd_mach_o_section *mo_sec
+ bfd_mach_o_section *mo_sec
= bfd_mach_o_get_mach_o_section (text_section);
mo_sec->flags &= ~BFD_MACH_O_S_ATTR_PURE_INSTRUCTIONS;
}
/* This will put at most 16 characters (terminated by a ',' or newline) from
the input stream into dest. If there are more than 16 chars before the
delimiter, a warning is given and the string is truncated. On completion of
- this function, input_line_pointer will point to the char after the ',' or
- to the newline.
-
+ this function, input_line_pointer will point to the char after the ',' or
+ to the newline.
+
It trims leading and trailing space. */
static int
SKIP_WHITESPACE ();
namstart = input_line_pointer;
- while ( (c = *input_line_pointer) != ','
+ while ( (c = *input_line_pointer) != ','
&& !is_end_of_line[(unsigned char) c])
input_line_pointer++;
{
int len = input_line_pointer - namstart; /* could be zero. */
- /* lose any trailing space. */
- while (len > 0 && namstart[len-1] == ' ')
+ /* lose any trailing space. */
+ while (len > 0 && namstart[len-1] == ' ')
len--;
if (len > 16)
{
/* Build (or get) a section from the mach-o description - which includes
optional definitions for type, attributes, alignment and stub size.
-
+
BFD supplies default values for sections which have a canonical name. */
#define SECT_TYPE_SPECIFIED 0x0001
static segT
obj_mach_o_make_or_get_sect (char * segname, char * sectname,
- unsigned int specified_mask,
+ unsigned int specified_mask,
unsigned int usectype, unsigned int usecattr,
unsigned int ualign, offsetT stub_size)
{
&& (specified_mask & SECT_ATTR_SPECIFIED)
&& (secattr & BFD_MACH_O_S_ATTR_PURE_INSTRUCTIONS))
flags |= SEC_CODE;
-
+
if (flags == SEC_NO_FLAGS
&& (specified_mask & SECT_ATTR_SPECIFIED)
&& (secattr & BFD_MACH_O_S_ATTR_DEBUG))
as_warn (_("failed to set flags for \"%s\": %s"),
bfd_section_name (stdoutput, sec),
bfd_errmsg (bfd_get_error ()));
-
+
strncpy (msect->segname, segname, sizeof (msect->segname));
strncpy (msect->sectname, sectname, sizeof (msect->sectname));
msect->align = secalign;
msect->flags = sectype | secattr;
-
+
if (sectype == BFD_MACH_O_S_ZEROFILL
|| sectype == BFD_MACH_O_S_GB_ZEROFILL)
seg_info (sec)->bss = 1;
White space is allowed everywhere between elements.
<segment> and <section> may be from 0 to 16 chars in length - they may
- contain spaces but leading and trailing space will be trimmed. It is
+ contain spaces but leading and trailing space will be trimmed. It is
mandatory that they be present (or that zero-length names are indicated
by ",,").
while (*input_line_pointer == '+');
/* Parse sizeof_stub. */
- if ((specified_mask & SECT_ATTR_SPECIFIED)
+ if ((specified_mask & SECT_ATTR_SPECIFIED)
&& *input_line_pointer == ',')
{
if (sectype != BFD_MACH_O_S_SYMBOL_STUBS)
sizeof_stub = get_absolute_expression ();
specified_mask |= SECT_STUB_SPECIFIED;
}
- else if ((specified_mask & SECT_ATTR_SPECIFIED)
+ else if ((specified_mask & SECT_ATTR_SPECIFIED)
&& sectype == BFD_MACH_O_S_SYMBOL_STUBS)
{
as_bad (_("missing sizeof_stub expression"));
}
}
- new_seg = obj_mach_o_make_or_get_sect (segname, sectname, specified_mask,
+ new_seg = obj_mach_o_make_or_get_sect (segname, sectname, specified_mask,
sectype, secattr, 0 /*align */,
sizeof_stub);
if (new_seg != NULL)
/* Parse variable definition, if present. */
if (*input_line_pointer == ',')
{
- /* Parse symbol, size [.align]
+ /* Parse symbol, size [.align]
We follow the method of s_common_internal, with the difference
that the symbol cannot be a duplicate-common. */
char *name;
char c;
char *p;
expressionS exp;
-
+
input_line_pointer++; /* Skip ',' */
SKIP_WHITESPACE ();
name = input_line_pointer;
goto done;
}
- SKIP_WHITESPACE ();
+ SKIP_WHITESPACE ();
if (*input_line_pointer == ',')
input_line_pointer++;
name, (long) size, (long) exp.X_add_number);
*p = c; /* Restore the termination char. */
-
- SKIP_WHITESPACE ();
+
+ SKIP_WHITESPACE ();
if (*input_line_pointer == ',')
{
align = (unsigned int) parse_align (0);
/* else just a section definition. */
specified_mask |= SECT_TYPE_SPECIFIED;
- new_seg = obj_mach_o_make_or_get_sect (segname, sectname, specified_mask,
+ new_seg = obj_mach_o_make_or_get_sect (segname, sectname, specified_mask,
BFD_MACH_O_S_ZEROFILL,
BFD_MACH_O_S_ATTR_NONE,
align, (offsetT) 0 /*stub size*/);
subseg_set (old_seg, 0);
}
-static segT
+static segT
obj_mach_o_segT_from_bfd_name (const char *nam, int must_succeed)
{
const mach_o_section_name_xlat *xlat;
msect->flags = xlat->macho_sectype | xlat->macho_secattr;
msect->align = xlat->sectalign;
- if ((msect->flags & BFD_MACH_O_SECTION_TYPE_MASK)
+ if ((msect->flags & BFD_MACH_O_SECTION_TYPE_MASK)
== BFD_MACH_O_S_ZEROFILL)
seg_info (sec)->bss = 1;
}
obj_mach_o_objc_section (int sect_index)
{
segT section;
-
+
#ifdef md_flush_pending_output
md_flush_pending_output ();
#endif
/* This could be moved to the tc-xx files, but there is so little dependency
there, that the code might as well be shared. */
-struct opt_tgt_sect
+struct opt_tgt_sect
{
const char *name;
unsigned x86_val;
addressT align = 0;
bfd_mach_o_asymbol *s;
- SKIP_WHITESPACE ();
+ SKIP_WHITESPACE ();
/* Both comm and lcomm take an optional alignment, as a power
of two between 1 and 15. */
if (bss_section == NULL)
{
bss_section = obj_mach_o_segT_from_bfd_name (BSS_SECTION_NAME, 1);
- seg_info (bss_section)->bss = 1;
+ seg_info (bss_section)->bss = 1;
}
bss_alloc (symbolP, size, align);
s->n_type = BFD_MACH_O_N_SECT;
OBJ_MACH_O_FILE_PROP_MAX
} obj_mach_o_file_properties;
-static void
+static void
obj_mach_o_fileprop (int prop)
{
if (prop < 0 || prop >= OBJ_MACH_O_FILE_PROP_MAX)
as_fatal (_("internal error: bad file property ID %d"), prop);
-
+
switch ((obj_mach_o_file_properties) prop)
{
case OBJ_MACH_O_FILE_PROP_SUBSECTS_VIA_SYMS:
obj_mach_o_subsections_by_symbols = 1;
- if (!bfd_set_private_flags (stdoutput,
+ if (!bfd_set_private_flags (stdoutput,
BFD_MACH_O_MH_SUBSECTIONS_VIA_SYMBOLS))
as_bad (_("failed to set subsections by symbols"));
demand_empty_rest_of_line ();
}
}
-/* Temporary markers for symbol reference data.
+/* Temporary markers for symbol reference data.
Lazy will remain in place. */
#define LAZY 0x01
#define REFE 0x02
int sectype = -1;
/* If the symbol is defined, then we can do more rigorous checking on
- the validity of the qualifiers. Otherwise, we are stuck with waiting
+ the validity of the qualifiers. Otherwise, we are stuck with waiting
until it's defined - or until write the file.
-
+
In certain cases (e.g. when a symbol qualifier is intended to introduce
an undefined symbol in a stubs section) we should check that the current
section is appropriate to the qualifier. */
}
*input_line_pointer = c;
- /* The indirect symbols are validated after the symbol table is
- frozen, we must make sure that if a local symbol is used as an
+ /* The indirect symbols are validated after the symbol table is
+ frozen, we must make sure that if a local symbol is used as an
indirect, it is promoted to a 'real' one. Fetching the bfd sym
achieves this. */
symbol_get_bfdsym (sym);
{ "debug_str", obj_mach_o_debug_section, 10}, /* extension. */
{ "debug_ranges", obj_mach_o_debug_section, 11}, /* extension. */
{ "debug_macro", obj_mach_o_debug_section, 12}, /* extension. */
-
+
{ "lazy_symbol_pointer", obj_mach_o_opt_tgt_section, 1},
{ "lazy_symbol_pointer2", obj_mach_o_opt_tgt_section, 2}, /* extension. */
{ "lazy_symbol_pointer3", obj_mach_o_opt_tgt_section, 3}, /* extension. */
{ "indirect_symbol", obj_mach_o_indirect_symbol, 0},
/* File flags. */
- { "subsections_via_symbols", obj_mach_o_fileprop,
+ { "subsections_via_symbols", obj_mach_o_fileprop,
OBJ_MACH_O_FILE_PROP_SUBSECTS_VIA_SYMS},
{NULL, NULL, 0}
/* We need to check the correspondence between some kinds of symbols and their
sections. Common and BSS vars will seen via the obj_macho_comm() function.
-
+
The earlier we can pick up a problem, the better the diagnostics will be.
-
+
However, when symbol type information is attached, the symbol section will
quite possibly be unknown. So we are stuck with checking (most of the)
validity at the time the file is written (unfortunately, then one doesn't
/* This is the base symbol type, that we mask in. */
base_type = obj_mach_o_type_for_symbol (s);
- sec = bfd_mach_o_get_mach_o_section (s->symbol.section);
+ sec = bfd_mach_o_get_mach_o_section (s->symbol.section);
if (sec != NULL)
sectype = sec->flags & BFD_MACH_O_SECTION_TYPE_MASK;
return 0;
base_type = obj_mach_o_type_for_symbol (s);
- sec = bfd_mach_o_get_mach_o_section (s->symbol.section);
+ sec = bfd_mach_o_get_mach_o_section (s->symbol.section);
if (sec != NULL)
sectype = sec->flags & BFD_MACH_O_SECTION_TYPE_MASK;
{
/* Anything here that should be added that is non-standard. */
s->n_desc &= ~BFD_MACH_O_REFERENCE_MASK;
- }
+ }
else if (s->symbol.udata.i == SYM_MACHO_FIELDS_NOT_VALIDATED)
{
/* Try to validate any combinations. */
/* It's a debug symbol. */
s->symbol.flags |= BSF_DEBUGGING;
-
+
/* We've set it - so check it, if you can, but don't try to create the
flags. */
s->symbol.udata.i = SYM_MACHO_FIELDS_NOT_VALIDATED;
}
}
-/* Handle mach-o subsections-via-symbols counting up frags belonging to each
+/* Handle mach-o subsections-via-symbols counting up frags belonging to each
sub-section. */
void
The native 'as' leaves the sections physically in the order they appear in
the source, and adjusts the section VMAs to meet the constraint.
-
+
We follow this for now - if nothing else, it makes comparison easier.
An alternative implementation would be to sort the sections as ld requires.
zerofill sections get VMAs after all others in their segment
GB zerofill get VMAs last.
-
+
As we go, we notice if we see any Zerofill or GB Zerofill sections, so that
we can skip the additional passes if there's nothing to do. */
/* We know the section size now - so make a vma for the section just
based on order. */
ms->size = bfd_get_section_size (sec);
-
+
/* Make sure that the align agrees, and set to the largest value chosen. */
ms->align = ms->align > bfd_align ? ms->align : bfd_align;
bfd_set_section_alignment (abfd, sec, ms->align);
-
+
p->vma += (1 << ms->align) - 1;
p->vma &= ~((1 << ms->align) - 1);
ms->addr = p->vma;
p->vma += ms->size;
}
-/* (potentially) three passes over the sections, setting VMA. We skip the
+/* (potentially) three passes over the sections, setting VMA. We skip the
{gb}zerofill passes if we didn't see any of the relevant sections. */
void obj_mach_o_post_relax_hook (void)
obj_mach_o_set_vma_data d;
memset (&d, 0, sizeof (d));
-
+
bfd_map_over_sections (stdoutput, obj_mach_o_set_section_vma, (char *) &d);
if ((d.vma_pass = d.zerofill_seen) != 0)
bfd_map_over_sections (stdoutput, obj_mach_o_set_section_vma, (char *) &d);
obj_mach_o_indirect_sym *isym;
obj_mach_o_indirect_sym *list = NULL;
obj_mach_o_indirect_sym *list_tail = NULL;
- unsigned long eltsiz =
+ unsigned long eltsiz =
bfd_mach_o_section_get_entry_size (abfd, ms);
for (isym = indirect_syms; isym != NULL; isym = isym->next)
as_fatal (_("internal error: failed to allocate %d indirect"
"symbol pointers"), nactual);
}
-
+
for (isym = list, n = 0; isym != NULL; isym = isym->next, n++)
{
sym = (bfd_mach_o_asymbol *)symbol_get_bfdsym (isym->sym);
/* Array is init to NULL & NULL signals a local symbol
If the section is lazy-bound, we need to keep the
reference to the symbol, since dyld can override.
-
+
Absolute symbols are handled specially. */
if (sym->symbol.section == bfd_abs_section_ptr)
ms->indirect_syms[n] = sym;
{
sym->n_desc &= ~LAZY;
/* ... it can be lazy, if not defined or hidden. */
- if ((sym->n_type & BFD_MACH_O_N_TYPE)
- == BFD_MACH_O_N_UNDF
+ if ((sym->n_type & BFD_MACH_O_N_TYPE)
+ == BFD_MACH_O_N_UNDF
&& ! (sym->n_type & BFD_MACH_O_N_PEXT)
&& (sym->n_type & BFD_MACH_O_N_EXT))
sym->n_desc |= lazy;
being made. */
int
-obj_mach_o_allow_local_subtract (expressionS * left ATTRIBUTE_UNUSED,
+obj_mach_o_allow_local_subtract (expressionS * left ATTRIBUTE_UNUSED,
expressionS * right ATTRIBUTE_UNUSED,
segT seg)
{
/* Symbol that corresponds to the subsection. */
symbolS *subsection;
};
-
+
#define OBJ_FRAG_TYPE struct obj_mach_o_frag_data
#define md_pre_output_hook obj_mach_o_pre_output_hook()
02110-1301, USA. */
#ifndef RL78_DEFS_H
-#define RL78_DEFS_H
+#define RL78_DEFS_H
/* Third operand to rl78_op. */
#define RL78REL_DATA 0
if (v & 1)
return 0;
return 1;
-
+
}
static void
;
float2_op_ni
- : { rx_check_float_support (); }
+ : { rx_check_float_support (); }
REG ',' REG
{ id24 (1, 0x83 + (sub_op << 2), 0); F ($2, 16, 4); F ($4, 20, 4); }
| { rx_check_float_support (); }
#define OPTION_REPLACE (OPTION_RELAX + 1)
#define OPTION_NOREPLACE (OPTION_REPLACE+1)
{ "replace", no_argument, NULL, OPTION_REPLACE },
- { "noreplace", no_argument, NULL, OPTION_NOREPLACE },
+ { "noreplace", no_argument, NULL, OPTION_NOREPLACE },
#endif
{ NULL, no_argument, NULL, 0 }
};
default:
gas_assert (size >= 1 && size <= 4);
}
-
+
pcrel = reloc_howto->pc_relative;
}
/* If this is a real relocation (as opposed to a lituse hint), then
the relocation width should match the operand width.
- Take care of -MDISP in operand table. */
+ Take care of -MDISP in operand table. */
else if (reloc < BFD_RELOC_UNUSED && reloc > 0)
{
reloc_howto_type *reloc_howto
if (basereg == alpha_gp_register &&
(symlen > 4 && strcmp (&symname [symlen - 4], "..lk") == 0))
return;
-
+
newtok[0] = tok[0];
set_tok_preg (newtok[2], basereg);
if (alpha_noat_on)
as_bad (_("macro requires $at register while noat in effect"));
- lituse = load_expression (AXP_REG_AT, &tok[1],
+ lituse = load_expression (AXP_REG_AT, &tok[1],
&basereg, &newtok[1], (const char *) opname);
}
else
fixS *fixp;
symbolS *linksym, *expsym;
expressionS e;
-
+
basesym = alpha_evax_proc->symbol;
/* @@ This assumes all entries in a given section will be of the same
segT current_seg = now_seg;
subsegT current_subseg = now_subseg;
int cur_size;
-
+
input_line_pointer++;
SKIP_WHITESPACE ();
sec_name = s_alpha_section_name ();
subseg_set (current_seg, current_subseg);
}
#endif
-
+
if (S_GET_VALUE (symbolP))
{
if (S_GET_VALUE (symbolP) != (valueT) size)
#endif
S_SET_EXTERNAL (symbolP);
}
-
+
#ifndef OBJ_EVAX
know (symbolP->sy_frag == &zero_address_frag);
#endif
{
no = 1;
str += 2;
- len -= 2;
+ len -= 2;
}
if (len == 3)
as_bad (_(".pdesc directive has no entry symbol"));
return;
}
-
+
entry_sym = make_expr_symbol (&exp);
entry_sym_name = S_GET_NAME (entry_sym);
-
+
/* Strip "..en". */
len = strlen (entry_sym_name);
if (len < 4 || strcmp (entry_sym_name + len - 4, "..en") != 0)
/* Define pdesc symbol. */
symbol_set_value_now (alpha_evax_proc->symbol);
-
+
/* Save bfd symbol of proc entry in function symbol. */
((struct evax_private_udata_struct *)
symbol_get_bfdsym (alpha_evax_proc->symbol)->udata.p)->enbsym
= symbol_get_bfdsym (entry_sym);
-
+
SKIP_WHITESPACE ();
if (*input_line_pointer++ != ',')
{
else
{
struct alpha_linkage_fixups *linkage_fixup;
-
+
p = frag_more (LKP_S_K_SIZE);
memset (p, 0, LKP_S_K_SIZE);
fixp = fix_new_exp
&& (mantissa & 0x1FFFFFFFl) == 0;
}
-/* Returns a double precision value casted to single precision
+/* Returns a double precision value casted to single precision
(ignoring the least significant bits in exponent and mantissa). */
static int
}
else
l = generic_bignum;
-
+
#if defined BFD_HOST_64_BIT
v =
((((((((bfd_int64_t) l[3] & LITTLENUM_MASK)
return TRUE;
}
else if ((v & ~0xFFFF) == 0 || (v & ~0xFFFF0000) == 0)
- {
+ {
/* The number may be loaded with a movw/movt instruction. */
int imm;
else
free (nbuf);
}
-
+
return FALSE;
}
char tmp_rp[16]="\0";
/* Add '(' and ')' to the reg pair, if its not present. */
- if (reg_name[0] != '(')
+ if (reg_name[0] != '(')
{
tmp_rp[0] = '(';
strcat (tmp_rp, reg_name);
return rreg->value.reg_val;
return nullregister;
-}
+}
/* Get the index register 'reg_name'. */
arelent * reloc;
/* If symbols are local and resolved, then no relocation needed. */
- if ( ((fixP->fx_addsy)
+ if ( ((fixP->fx_addsy)
&& (S_GET_SEGMENT (fixP->fx_addsy) == absolute_section))
- || ((fixP->fx_subsy)
+ || ((fixP->fx_subsy)
&& (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section)))
return NULL;
else if (strneq (input_line_pointer, "@GOT", 4)
|| strneq (input_line_pointer, "@got", 4))
{
- if ((strneq (input_line_pointer, "+", 1))
+ if ((strneq (input_line_pointer, "+", 1))
|| (strneq (input_line_pointer, "-", 1)))
as_warn (_("GOT bad expression with %s."), input_line_pointer);
int size;
reloc_howto = bfd_reloc_type_lookup (stdoutput, insn->rtype);
-
+
if (!reloc_howto)
abort ();
extern void cr16_cons_fix_new (struct frag *, int, int, struct expressionS *,
bfd_reloc_code_real_type);
/* This is called by emit_expr when creating a reloc for a cons.
- We could use the definition there, except that we want to handle
+ We could use the definition there, except that we want to handle
the CR16 reloc type specially, rather than the BFD_RELOC type. */
#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \
cr16_cons_fix_new (FRAG, OFF, LEN, EXP, RELOC)
-/* Give an error if a frag containing code is not aligned to a 2-byte
+/* Give an error if a frag containing code is not aligned to a 2-byte
boundary. */
#define md_frag_check(FRAGP) \
if ((FRAGP)->has_code \
out_insnp->opcode |= regno << 12;
out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_8;
continue;
-
+
case 'O':
/* A BDAP expression for any size, "expr,R". */
if (! cris_get_expression (&s, &prefixp->expr))
|| iver == cris_ver_v8_10
|| iver == cris_ver_v10
|| iver == cris_ver_v10p);
-
+
case arch_crisv32:
return
(iver == cris_ver_version_all
OP_NOT_EVEN, /* Operand is Odd number, should be even. */
OP_ILLEGAL_DISPU4, /* Operand is not within DISPU4 range. */
OP_ILLEGAL_CST4, /* Operand is not within CST4 range. */
- OP_NOT_UPPER_64KB /* Operand is not within the upper 64KB
+ OP_NOT_UPPER_64KB /* Operand is not within the upper 64KB
(0xFFFF0000-0xFFFFFFFF). */
}
op_err;
/* Set up a hash table for the instructions. */
if ((crx_inst_hash = hash_new ()) == NULL)
as_fatal (_("Virtual memory exhausted"));
-
+
while (crx_instruction[i].mnemonic != NULL)
{
const char *mnemonic = crx_instruction[i].mnemonic;
linkrelax = 1;
}
-/* Process constants (immediate/absolute)
+/* Process constants (immediate/absolute)
and labels (jump targets/Memory locations). */
static void
input_line_pointer = str;
expression (&crx_ins->exp);
-
+
switch (crx_ins->exp.X_op)
{
case O_big:
case arg_idxr:
crx_ins->rtype = BFD_RELOC_CRX_REGREL22;
break;
-
+
case arg_c:
if (IS_INSN_MNEMONIC ("bal") || IS_INSN_TYPE (DCR_BRANCH_INS))
crx_ins->rtype = BFD_RELOC_CRX_REL16;
else if (IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (COP_BRANCH_INS))
crx_ins->rtype = BFD_RELOC_CRX_REL8_CMP;
break;
-
+
case arg_ic:
if (IS_INSN_TYPE (ARITH_INS))
crx_ins->rtype = BFD_RELOC_CRX_IMM32;
case arg_c: /* Case 0x18. */
/* Set constant. */
process_label_constant (operandS, crx_ins);
-
+
if (cur_arg->type != arg_ic)
cur_arg->type = arg_c;
break;
operandE++;
*operandE = '\0';
process_label_constant (operandS, crx_ins);
- operandS = operandE;
+ operandS = operandE;
case arg_rbase: /* Case (r1). */
operandS++;
/* Set register base. */
*operandE = '\0';
process_label_constant (operandS, crx_ins);
operandS = ++operandE;
-
+
/* Set register base. */
while ((*operandE != ',') && (! ISSPACE (*operandE)))
operandE++;
default:
break;
}
-
+
if (strchr (operand, '(') != NULL)
{
if (strchr (operand, ',') != NULL
set_operand (operand, crx_ins);
}
-/* Parse the various operands. Each operand is then analyzed to fillup
+/* Parse the various operands. Each operand is then analyzed to fillup
the fields in the crx_ins data structure. */
static void
return 0;
}
-/* Post-Increment instructions, as well as Store-Immediate instructions, are a
- sub-group within load/stor instruction groups.
- Therefore, when parsing a Post-Increment/Store-Immediate insn, we have to
- advance the instruction pointer to the start of that sub-group (that is, up
+/* Post-Increment instructions, as well as Store-Immediate instructions, are a
+ sub-group within load/stor instruction groups.
+ Therefore, when parsing a Post-Increment/Store-Immediate insn, we have to
+ advance the instruction pointer to the start of that sub-group (that is, up
to the first instruction of that type).
Otherwise, the insn will be mistakenly identified as of type LD_STOR_INS. */
static void
handle_LoadStor (const char *operands)
{
- /* Post-Increment instructions precede Store-Immediate instructions in
- CRX instruction table, hence they are handled before.
+ /* Post-Increment instructions precede Store-Immediate instructions in
+ CRX instruction table, hence they are handled before.
This synchronization should be kept. */
/* Assuming Post-Increment insn has the following format :
break;
}
- /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
- always filling the upper part of output_opcode[1]. If we mistakenly
+ /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
+ always filling the upper part of output_opcode[1]. If we mistakenly
write it to output_opcode[0], the constant prefix (that is, 'match')
will be overridden.
0 1 2 3
return i;
}
-/* Verify that the number NUM can be represented in BITS bits (that is,
- within its permitted range), based on the instruction's FLAGS.
+/* Verify that the number NUM can be represented in BITS bits (that is,
+ within its permitted range), based on the instruction's FLAGS.
If UPDATE is nonzero, update the value of NUM if necessary.
Return OP_LEGAL upon success, actual error type upon failure. */
{
int is_dispu4 = 0;
- uint32_t mul = (instruction->flags & DISPUB4 ? 1
+ uint32_t mul = (instruction->flags & DISPUB4 ? 1
: instruction->flags & DISPUW4 ? 2
: instruction->flags & DISPUD4 ? 4
: 0);
-
+
for (bin = 0; bin < cst4_maps; bin++)
{
if (value == mul * bin)
/* Assemble a single instruction:
INSN is already parsed (that is, all operand values and types are set).
- For instruction to be assembled, we need to find an appropriate template in
+ For instruction to be assembled, we need to find an appropriate template in
the instruction table, meeting the following conditions:
1: Has the same number of operands.
2: Has the same operand types.
/* In some case, same mnemonic can appear with different instruction types.
For example, 'storb' is supported with 3 different types :
LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS.
- We assume that when reaching this point, the instruction type was
+ We assume that when reaching this point, the instruction type was
pre-determined. We need to make sure that the type stays the same
during a search for matching instruction. */
ins_type = CRX_INS_TYPE(instruction->flags);
{
/* Reverse the operand indices for certain opcodes:
Index 0 -->> 1
- Index 1 -->> 0
+ Index 1 -->> 0
Other index -->> stays the same. */
- int j = instruction->flags & REVERSE_MATCH ?
- i == 0 ? 1 :
- i == 1 ? 0 : i :
+ int j = instruction->flags & REVERSE_MATCH ?
+ i == 0 ? 1 :
+ i == 1 ? 0 : i :
i;
- /* Only check range - don't update the constant's value, since the
- current instruction may not be the last we try to match.
- The constant's value will be updated later, right before printing
+ /* Only check range - don't update the constant's value, since the
+ current instruction may not be the last we try to match.
+ The constant's value will be updated later, right before printing
it to the object file. */
- if ((insn->arg[j].X_op == O_constant)
- && (op_error = check_range (&insn->arg[j].constant, cur_size[j],
+ if ((insn->arg[j].X_op == O_constant)
+ && (op_error = check_range (&insn->arg[j].constant, cur_size[j],
cur_flags[j], 0)))
{
if (invalid_const == -1)
}
goto next_insn;
}
- /* For symbols, we make sure the relocation size (which was already
+ /* For symbols, we make sure the relocation size (which was already
determined) is sufficient. */
else if ((insn->arg[j].X_op == O_symbol)
- && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize
+ && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize
> cur_size[j]))
goto next_insn;
}
as_bad (_("Invalid CST4 operand value (arg %d)"), invalid_const);
break;
case OP_NOT_UPPER_64KB:
- as_bad (_("Operand value is not within upper 64 KB (arg %d)"),
+ as_bad (_("Operand value is not within upper 64 KB (arg %d)"),
invalid_const);
break;
default:
break;
}
}
-
+
return 0;
}
else
/* Make further checkings (such that couldn't be made earlier).
Warn the user if necessary. */
warn_if_needed (insn);
-
+
/* Check whether we need to adjust the instruction pointer. */
if (adjust_if_needed (insn))
- /* If instruction pointer was adjusted, we need to update
+ /* If instruction pointer was adjusted, we need to update
the size of the current template operands. */
GET_CURRENT_SIZE;
for (i = 0; i < insn->nargs; i++)
{
- int j = instruction->flags & REVERSE_MATCH ?
- i == 0 ? 1 :
- i == 1 ? 0 : i :
+ int j = instruction->flags & REVERSE_MATCH ?
+ i == 0 ? 1 :
+ i == 1 ? 0 : i :
i;
/* This time, update constant value before printing it. */
- if ((insn->arg[j].X_op == O_constant)
- && (check_range (&insn->arg[j].constant, cur_size[j],
+ if ((insn->arg[j].X_op == O_constant)
+ && (check_range (&insn->arg[j].constant, cur_size[j],
cur_flags[j], 1) != OP_LEGAL))
as_fatal (_("Illegal operand (arg %d)"), j+1);
}
for (i = 0; i < insn->nargs; i++)
{
cur_arg_num = i;
- print_operand (cur_size[i], instruction->operands[i].shift,
+ print_operand (cur_size[i], instruction->operands[i].shift,
&insn->arg[i]);
}
}
void
warn_if_needed (ins *insn)
{
- /* If the post-increment address mode is used and the load/store
- source register is the same as rbase, the result of the
+ /* If the post-increment address mode is used and the load/store
+ source register is the same as rbase, the result of the
instruction is undefined. */
if (IS_INSN_TYPE (LD_STOR_INS_INC))
{
/* Enough to verify that one of the arguments is a simple reg. */
if ((insn->arg[0].type == arg_r) || (insn->arg[1].type == arg_r))
if (insn->arg[0].r == insn->arg[1].r)
- as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
+ as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
insn->arg[0].r);
}
as_bad (_("`%s' has undefined result"), ins_parse);
}
- /* If the rptr register is specified as one of the registers to be loaded,
+ /* If the rptr register is specified as one of the registers to be loaded,
the final contents of rptr are undefined. Thus, we issue an error. */
if (instruction->flags & NO_RPTR)
{
if ((1 << getreg_image (insn->arg[0].r)) & insn->arg[1].constant)
- as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
+ as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
getreg_image (insn->arg[0].r));
}
}
-/* In some cases, we need to adjust the instruction pointer although a
+/* In some cases, we need to adjust the instruction pointer although a
match was already found. Here, we gather all these cases.
Returns 1 if instruction pointer was adjusted, otherwise 0. */
}
}
- /* Optimization: Omit a zero displacement in bit operations,
+ /* Optimization: Omit a zero displacement in bit operations,
saving 2-byte encoding space (e.g., 'cbitw $8, 0(r1)'). */
if (IS_INSN_TYPE (CSTBIT_INS))
{
{
if (((cr = get_copregister (reg_name)) == nullcopregister)
|| (crx_copregtab[cr-MAX_REG].type != CRX_CS_REGTYPE))
- as_fatal (_("Illegal register `%s' in cop-special-register list"),
+ as_fatal (_("Illegal register `%s' in cop-special-register list"),
reg_name);
mask_reg (getreg_image (cr - cs0), &mask);
}
else if (((r = get_register (reg_name)) == nullregister)
|| (crx_regtab[r].type != CRX_U_REGTYPE))
as_fatal (_("Illegal register `%s' in user register list"), reg_name);
-
- mask_reg (getreg_image (r - u0), &mask);
+
+ mask_reg (getreg_image (r - u0), &mask);
}
/* General purpose register r<N>. */
else
#define DWARF2_LINE_MIN_INSN_LENGTH 2
/* This is called by emit_expr when creating a reloc for a cons.
- We could use the definition there, except that we want to handle
+ We could use the definition there, except that we want to handle
the CRX reloc type specially, rather than the BFD_RELOC type. */
#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \
(void) RELOC, \
: LEN == 4 ? BFD_RELOC_CRX_NUM32 \
: BFD_RELOC_NONE);
-/* Give an error if a frag containing code is not aligned to a 2-byte
+/* Give an error if a frag containing code is not aligned to a 2-byte
boundary. */
#define md_frag_check(FRAGP) \
if ((FRAGP)->has_code \
continue;
}
- the_insn.reloc = (the_insn.HI) ? RELOC_DLX_HI16
+ the_insn.reloc = (the_insn.HI) ? RELOC_DLX_HI16
: (the_insn.LO ? RELOC_DLX_LO16 : RELOC_DLX_16);
the_insn.reloc_offset = 2;
the_insn.size = 2;
Boston, MA 02110-1301, USA. */
#include "as.h"
-#include "subsegs.h"
+#include "subsegs.h"
#include "symcat.h"
#include "opcodes/frv-desc.h"
#include "opcodes/frv-opc.h"
VLIW_BRANCH_HAS_NOPS /* A Branch that requires NOPS. */
};
-/* We're going to use these in the fr_subtype field to mark
+/* We're going to use these in the fr_subtype field to mark
whether to keep inserted nops. */
#define NOP_KEEP 1 /* Keep these NOPS. */
const char comment_chars[] = ";";
const char line_comment_chars[] = "#";
-const char line_separator_chars[] = "!";
+const char line_separator_chars[] = "!";
const char EXP_CHARS[] = "eE";
const char FLT_CHARS[] = "dD";
fprintf (stream, _(" Record the cpu type\n"));
fprintf (stream, _("-mtomcat-stats Print out stats for tomcat workarounds\n"));
fprintf (stream, _("-mtomcat-debug Debug tomcat workarounds\n"));
-}
+}
\f
void
md_begin (void)
{
/* Initialize the `cgen' interface. */
-
+
/* Set the machine number and endian. */
gas_cgen_cpu_desc = frv_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
CGEN_CPU_OPEN_ENDIAN,
}
/* Identify the following cases:
-
+
1) A VLIW insn that contains both a branch and the branch destination.
This requires the insertion of two vliw instructions before the
branch. The first consists of two nops. The second consists of
a single nop.
-
+
2) A single instruction VLIW insn which is the destination of a branch
that is in the next VLIW insn. This requires the insertion of a vliw
insn containing two nops before the branch.
-
+
3) A double instruction VLIW insn which contains the destination of a
branch that is in the next VLIW insn. This requires the insertion of
a VLIW insn containing a single nop before the branch.
-
+
4) A single instruction VLIW insn which contains branch destination (x),
followed by a single instruction VLIW insn which does not contain
the branch to (x), followed by a VLIW insn which does contain the branch
to (x). This requires the insertion of a VLIW insn containing a single
nop before the VLIW instruction containing the branch.
-
+
*/
#define FRV_IS_NOP(insn) (insn.buffer[0] == FRV_NOP_PACK || insn.buffer[0] == FRV_NOP_NOPACK)
#define FRV_NOP_PACK 0x00880000 /* ori.p gr0,0,gr0 */
{
/* A Vliw insn containing a single nop insn. */
VLIW_SINGLE_NOP,
-
+
/* A Vliw insn containing two nop insns. */
VLIW_DOUBLE_NOP,
- /* Two vliw insns. The first containing two nop insns.
+ /* Two vliw insns. The first containing two nop insns.
The second contain a single nop insn. */
VLIW_DOUBLE_THEN_SINGLE_NOP
};
pack_prev = TRUE;
prev_insn = curr_insn;
curr_insn = curr_insn->next;
- }
+ }
while (curr_vliw && curr_vliw != vliw_to_split)
{
frv_adjust_vliw_count (second_part);
single_nop->next = second_part;
-
+
vliw_to_split->next = single_nop;
prev_insn->next = NULL;
-
+
return_me = second_part;
frv_adjust_vliw_count (vliw_to_split);
}
second_part->insn_list->type = VLIW_BRANCH_HAS_NOPS;
second_part->next = vliw_to_split->next;
frv_adjust_vliw_count (second_part);
-
+
double_nop->next = second_part;
-
+
vliw_to_split->next = single_nop;
prev_insn->next = NULL;
frv_adjust_vliw_count (vliw_to_split);
-
+
return_me = second_part;
}
break;
prev_vliw->next = double_nop;
else
vliw_chain_top = double_nop;
-
+
single_nop->next = vliw_to_split;
return_me = vliw_to_split;
vliw_to_split->insn_list->type = VLIW_BRANCH_HAS_NOPS;
}
/* The branch is in the middle of this vliw insn. Split into first and
- second parts. Insert the nop vliws in between. */
+ second parts. Insert the nop vliws in between. */
second_part->insn_list = insert_before_insn;
second_part->insn_list->type = VLIW_BRANCH_HAS_NOPS;
second_part->next = vliw_to_split->next;
tomcat_doubles++;
goto workaround_top;
}
- else if (vliw2
+ else if (vliw2
&& vliw2->insn_count == 1
&& (temp_insn = frv_find_in_vliw (VLIW_BRANCH_TYPE, vliw3, vliw1->insn_list->sym)) != NULL)
{
case FRV_INSN_CMQMULHU:
case FRV_INSN_MMACHS:
case FRV_INSN_MMRDHS:
- case FRV_INSN_CMMACHS:
+ case FRV_INSN_CMMACHS:
case FRV_INSN_MQMACHS:
case FRV_INSN_CMQMACHS:
case FRV_INSN_MQXMACHS:
insn.insn = frv_cgen_assemble_insn
(gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, &errmsg);
-
+
if (!insn.insn)
{
as_bad ("%s", errmsg);
return;
}
-
+
/* If the cpu is tomcat, then we need to insert nops to workaround
hardware limitations. We need to keep track of each vliw unit
and examine the length of the unit and the individual insns
{
/* If we've just finished a VLIW insn OR this is a branch,
then start up a new frag. Fill it with nops. We will get rid
- of those that are not required after we've seen all of the
+ of those that are not required after we've seen all of the
instructions but before we start resolving fixups. */
if ( !FRV_IS_NOP (insn)
&& (frv_is_branch_insn (insn.insn) || insn.fields.f_pack))
previous_vliw_chain = current_vliw_chain;
current_vliw_chain = NULL;
current_vliw_insn = NULL;
- }
+ }
}
}
/* The syntax in the manual says constants begin with '#'.
We just ignore it. */
-void
+void
md_operand (expressionS *expressionP)
{
if (* input_line_pointer == '#')
default:
case NOP_DELETE:
return 0;
- }
-}
+ }
+}
/* *fragP has been relaxed to its final size, and now needs to have
the bytes inside it modified to conform to the new size.
case NOP_KEEP:
fragP->fr_fix = fragP->fr_var;
fragP->fr_var = 0;
- return;
+ return;
}
}
\f
case FRV_OPERAND_U12:
return BFD_RELOC_FRV_GPRELU12;
- default:
+ default:
break;
}
return BFD_RELOC_NONE;
do
{
bfd_reloc_code_real_type reloc_type = BFD_RELOC_CTOR;
-
+
if (strncasecmp (input_line_pointer, "funcdesc(", 9) == 0)
{
input_line_pointer += 9;
vliw_insn_list_entry = frv_insert_vliw_insn(DONT_COUNT);
vliw_insn_list_entry->type = VLIW_LABEL_TYPE;
- vliw_insn_list_entry->sym = this_label;
+ vliw_insn_list_entry->sym = this_label;
}
fixS *
&& current_vliw_insn->type == VLIW_BRANCH_TYPE
&& exp != NULL)
current_vliw_insn->sym = exp->X_add_symbol;
-
+
return fixP;
}
prev_buffer[0] = 0;
nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode);
-
+
h8_instructions = (struct h8_instruction *)
xmalloc (nopcodes * sizeof (struct h8_instruction));
*reg = 7;
return len;
}
- if (len == 3 &&
- TOLOWER (src[0]) == 'c' &&
- TOLOWER (src[1]) == 'c' &&
+ if (len == 3 &&
+ TOLOWER (src[0]) == 'c' &&
+ TOLOWER (src[1]) == 'c' &&
TOLOWER (src[2]) == 'r')
{
*mode = CCR;
*reg = 0;
return len;
}
- if (len == 3 &&
- TOLOWER (src[0]) == 'e' &&
- TOLOWER (src[1]) == 'x' &&
+ if (len == 3 &&
+ TOLOWER (src[0]) == 'e' &&
+ TOLOWER (src[1]) == 'x' &&
TOLOWER (src[2]) == 'r')
{
*mode = EXR;
*reg = 1;
return len;
}
- if (len == 3 &&
- TOLOWER (src[0]) == 'v' &&
- TOLOWER (src[1]) == 'b' &&
+ if (len == 3 &&
+ TOLOWER (src[0]) == 'v' &&
+ TOLOWER (src[1]) == 'b' &&
TOLOWER (src[2]) == 'r')
{
*mode = VBR;
*reg = 6;
return len;
}
- if (len == 3 &&
- TOLOWER (src[0]) == 's' &&
- TOLOWER (src[1]) == 'b' &&
+ if (len == 3 &&
+ TOLOWER (src[0]) == 's' &&
+ TOLOWER (src[1]) == 'b' &&
TOLOWER (src[2]) == 'r')
{
*mode = SBR;
/* Gross. Gross. ldm and stm have a format not easily handled
by get_operand. We deal with it explicitly here. */
- if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' &&
+ if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' &&
ISDIGIT (src[2]) && src[3] == '-' &&
TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6]))
{
}
if (mode
&& src[len + 2] == ','
- && TOLOWER (src[len + 3]) != 'p'
+ && TOLOWER (src[len + 3]) != 'p'
&& TOLOWER (src[len + 4]) != 'c'
&& src[len + 5] != ')')
{
*ptr = parse_exp (src + 1, op);
return;
}
- else if (strncmp (src, "mach", 4) == 0 ||
+ else if (strncmp (src, "mach", 4) == 0 ||
strncmp (src, "macl", 4) == 0 ||
- strncmp (src, "MACH", 4) == 0 ||
+ strncmp (src, "MACH", 4) == 0 ||
strncmp (src, "MACL", 4) == 0)
{
op->reg = TOLOWER (src[3]) == 'l';
}
else if ((operand[1].mode & MODE) == LOWREG)
{
- switch (operand[1].mode & SIZE)
+ switch (operand[1].mode & SIZE)
{
case L_8:
operand[0].mode = (operand[0].mode & ~MODE) | INDEXB;
if (!Hmode && this_try->opcode->available != AV_H8)
as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"),
this_try->opcode->name);
- else if (!Smode
- && this_try->opcode->available != AV_H8
+ else if (!Smode
+ && this_try->opcode->available != AV_H8
&& this_try->opcode->available != AV_H8H)
as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"),
this_try->opcode->name);
- else if (!SXmode
+ else if (!SXmode
&& this_try->opcode->available != AV_H8
&& this_try->opcode->available != AV_H8H
&& this_try->opcode->available != AV_H8S)
/* To be compatible with the proposed H8 ELF format, we
want the relocation's offset to point to the first byte
that will be modified, not to the start of the instruction. */
-
+
if ((operand->mode & SIZE) == L_32)
{
where = 2;
/* This jmp may be a jump or a branch. */
- check_operand (operand + i,
- SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff,
+ check_operand (operand + i,
+ SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff,
"@");
if (operand[i].exp.X_add_number & 1)
is safe. get_specific() will relax L_24 into L_32 where
necessary. */
if (Hmode
- && !Nmode
+ && !Nmode
&& ((((addressT) operand->exp.X_add_number + 0x8000)
& 0xffffffff) > 0xffff
|| operand->exp.X_add_symbol != 0
waste space padding out to alignments. The four pointers
longlong_poolP, word_poolP, etc. point to a symbol labeling the
start of each pool part.
-
+
lit_pool_num increments from zero to infinity and uniquely id's
-- its used to generate the *_poolP symbol name. */
{ STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
CPU_BDVER4_FLAGS, 0, 0 },
{ STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
- CPU_ZNVER1_FLAGS, 0, 0 },
+ CPU_ZNVER1_FLAGS, 0, 0 },
{ STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
CPU_BTVER1_FLAGS, 0, 0 },
{ STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
static void s_atmp (int);
static void s_align_wrapper (int);
static int i860_get_expression (char *);
-static bfd_reloc_code_real_type obtain_reloc_for_imm16 (fixS *, long *);
+static bfd_reloc_code_real_type obtain_reloc_for_imm16 (fixS *, long *);
#ifdef DEBUG_I860
static void print_insn (struct i860_it *);
#endif
}
/* Handle ".align" directive depending on syntax mode.
- AT&T/SVR4 syntax uses the standard align directive. However,
+ AT&T/SVR4 syntax uses the standard align directive. However,
the Intel syntax additionally allows keywords for the alignment
parameter: ".align type", where type is one of {.short, .long,
.quad, .single, .double} representing alignments of 2, 4,
strncpy (parm, " 4", 7);
else if (strncmp (parm, ".double", 7) == 0)
strncpy (parm, " 8", 7);
-
+
while (*input_line_pointer == ' ')
++input_line_pointer;
}
the_insn.expand = insn->expand;
fc++;
-
+
continue;
}
else
i860_check_label (symbolS *labelsym)
{
/* At this point, the current line pointer is sitting on the character
- just after the first colon on the label. */
+ just after the first colon on the label. */
if (target_intel_syntax && *input_line_pointer == ':')
{
S_SET_EXTERNAL (labelsym);
int numbits, /* # bits of displacement (13 for COBR, 24 for CTRL). */
int var_frag,/* 1 if varying length code fragment should be emitted;
0 if an address fix should be emitted. */
- int callj) /* 1 if callj relocation should be done; else 0. */
+ int callj) /* 1 if callj relocation should be done; else 0. */
{
expressionS e; /* Parsed expression. */
fixS *fixP; /* Structure describing needed address fix. */
}
/* get_ispec: parse a memory operand for an index specification
-
+
Here, an "index specification" is taken to be anything surrounded
by square brackets and NOT followed by anything else.
static char *
get_ispec (char *textP) /* Pointer to memory operand from source instruction, no white space. */
-
+
{
/* Points to start of index specification. */
char *start;
ldconst 64,<reg> -> shlo 8,3,<reg>
ldconst -1,<reg> -> subo 1,0,<reg>
ldconst -31,<reg> -> subo 31,0,<reg>
-
+
Anything else becomes:
lda xxx,<reg>. */
n = offs (e);
passed fixup structure. */
int
-reloc_callj (fixS *fixP) /* Relocation that can be done at assembly time. */
+reloc_callj (fixS *fixP) /* Relocation that can be done at assembly time. */
{
/* Points to the binary for the instruction being relocated. */
char *where;
return reg >= 64 && reg <= 111;
}
-/* Determine if application register REGNUM resides only in the memory
+/* Determine if application register REGNUM resides only in the memory
unit (as opposed to the integer unit). */
static int
ar_is_only_in_memory_unit (int reg)
/* Set expression which points to start of unwind descriptor area. */
unwind.info = expr_build_dot ();
-
+
frag_var (rs_machine_dependent, size, size, 0, 0,
(offsetT) (long) unwind.personality_routine,
(char *) list);
if (e->X_op == O_constant)
{
/* 5-bit signed scaled by 64 */
- if ((e->X_add_number <= ( 0xf << 6 ))
+ if ((e->X_add_number <= ( 0xf << 6 ))
&& (e->X_add_number >= -( 0x10 << 6 )))
{
-
+
/* Must be a multiple of 64 */
if ((e->X_add_number & 0x3f) != 0)
as_warn (_("stride must be a multiple of 64; lower 6 bits ignored"));
if (e->X_op == O_constant)
{
/* 6-bit unsigned biased by 1 -- count 0 is meaningless */
- if ((e->X_add_number <= 64)
+ if ((e->X_add_number <= 64)
&& (e->X_add_number > 0) )
{
return OPERAND_MATCH;
for (; ; ++i)
{
- if (i < NELEMS (CURR_SLOT.opnd))
+ if (i < NELEMS (CURR_SLOT.opnd))
{
sep = parse_operand_maybe_eval (CURR_SLOT.opnd + i, '=',
idesc->operands[i]);
as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
_("Missing '}' at end of file"));
}
-
+
know (md.num_slots_in_use < NUM_SLOTS);
t0 = end_of_insn_group | (template_val << 1) | (insn[0] << 5) | (insn[1] << 46);
print_prmask (qp_mutexes[i].prmask);
fprintf (stderr, "\n");
}
-
+
/* Deal with the old mutex with more than 3+ PRs only if
the new mutex on the same execution path with it.
if (add == 0
&& (qp_mutexes[i].prmask & mask) == mask)
add = 1;
-
+
qp_mutexes[i].prmask &= ~mask;
if (qp_mutexes[i].prmask & (qp_mutexes[i].prmask - 1))
{
i++;
}
}
-
+
if (keep == 0)
/* Remove the mutex. */
qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
{
enum ia64_opnd opnd1, opnd2;
int rop;
-
+
opnd1 = idesc->operands[0];
opnd2 = idesc->operands[1];
if (opnd1 == IA64_OPND_AR3)
bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
p = fragp->fr_literal + fragp->fr_fix;
- /* If no paddings are needed, we check if we need a stop bit. */
+ /* If no paddings are needed, we check if we need a stop bit. */
if (!bytes && fragp->tc_frag_data)
{
if (fragp->fr_fix < 16)
h = (struct alias *) xmalloc (sizeof (struct alias));
as_where (&h->file, &h->line);
h->name = name;
-
+
error_string = hash_jam (ahash, alias, (void *) h);
if (error_string)
{
bname = xstrdup (lbasename (out_file_name));
if ((p = strrchr (bname, '.')))
*p = '\0';
-
+
/* VMS note header is 24 bytes long. */
p = frag_more (8 + 8 + 8);
number_to_chars_littleendian (p + 0, 8, 8);
Boston, MA 02110-1301, USA. */
#include "as.h"
-#include "subsegs.h"
+#include "subsegs.h"
#include "symcat.h"
#include "opcodes/ip2k-desc.h"
#include "opcodes/ip2k-opc.h"
const char comment_chars[] = ";";
const char line_comment_chars[] = "#";
-const char line_separator_chars[] = "";
+const char line_separator_chars[] = "";
const char EXP_CHARS[] = "eE";
const char FLT_CHARS[] = "dD";
OPTION_CPU_IP2022EXT
};
-struct option md_longopts[] =
+struct option md_longopts[] =
{
{ "mip2022", no_argument, NULL, OPTION_CPU_IP2022 },
{ "mip2022ext", no_argument, NULL, OPTION_CPU_IP2022EXT },
md_begin (void)
{
/* Initialize the `cgen' interface. */
-
+
/* Set the machine number and endian. */
gas_cgen_cpu_desc = ip2k_cgen_cpu_open (CGEN_CPU_OPEN_MACHS,
ip2k_mach_bitmask,
{
as_fatal (_("relaxation not supported\n"));
return 1;
-}
+}
/* *fragP has been relaxed to its final size, and now needs to have
word alignment should be forced. */
if (flags & SEC_CODE)
force_code_align = 1;
-
+
return flags;
}
Boston, MA 02111-1307, USA. */
#include "as.h"
-#include "subsegs.h"
+#include "subsegs.h"
#include "symcat.h"
#include "opcodes/m32c-desc.h"
#include "opcodes/m32c-opc.h"
md_show_usage (FILE * stream)
{
fprintf (stream, _(" M32C specific command line options:\n"));
-}
+}
static void
s_bss (int ignore ATTRIBUTE_UNUSED)
if (s[0] == '[' && s[1] == '[')
indirection[operand] = relative;
}
-
+
if (indirection[1] == none && indirection[2] == none)
return FALSE;
-
+
operand = 1;
ns_len = strlen (str);
new_str = (char*) xmalloc (ns_len);
ns = new_str;
ns_end = ns + ns_len;
-
+
for (s = str; *s; s++)
{
if (s[0] == ',')
operand = 2;
-
+
if (s[0] == '[' && ! brace_n[operand])
{
brace_n[operand] += 1;
if (indirection[operand] != none)
continue;
}
-
+
else if (s[0] == '[' && brace_n[operand])
{
brace_n[operand] += 1;
{
fprintf (stderr, "Unmatched [[operand-%d]] %d\n", operand, brace_n[operand]);
}
-
+
if (indirection[1] != none && indirection[2] != none)
md_assemble ("src-dest-indirect");
else if (indirection[1] != none)
insn.insn = m32c_cgen_assemble_insn
(gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
-
+
if (!insn.insn)
{
as_bad ("%s", errmsg);
/* The syntax in the manual says constants begin with '#'.
We just ignore it. */
-void
+void
md_operand (expressionS * exp)
{
/* In case of a syntax error, escape back to try next syntax combo. */
}
return subtype_mappings[fragP->fr_subtype].bytes - (fragP->fr_fix - where);
-}
+}
/* *fragP has been relaxed to its final size, and now needs to have
the bytes inside it modified to conform to the new size.
|| fx->fx_r_type == BFD_RELOC_M32C_RL_2ADDR)
{
arelent * reloc;
-
+
reloc = xmalloc (sizeof (* reloc));
-
+
reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fx->fx_addsy);
reloc->address = fx->fx_frag->fr_address + fx->fx_where;
{
arelent * reloc;
bfd_reloc_code_real_type code;
-
+
reloc = xmalloc (sizeof (* reloc));
-
+
reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
bfd_set_error (bfd_error_bad_value);
}
}
-
+
code = fixP->fx_r_type;
if (pic_code)
{
printf(" => %s",bfd_get_reloc_code_name(code));
#endif
}
-
+
reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
#ifdef DEBUG_PIC
fixP->fx_r_type, bfd_get_reloc_code_name (code));
return NULL;
}
-
+
/* Use fx_offset for these cases. */
if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
|| fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
reloc->addend = fixP->fx_offset;
else
reloc->addend = fixP->fx_addnumber;
-
+
return reloc;
}
#define md_flush_pending_output() m32r_flush_pending_output ()
extern void m32r_flush_pending_output (void);
-
+
#define elf_tc_final_processing m32r_elf_final_processing
extern void m32r_elf_final_processing (void);
if (!check_range (val, M6812_OP_IDX))
as_bad (_("Offset out of 16-bit range: %ld."), val);
- if (move_insn && !(val >= -16 && val <= 15)
- && ((!(mode & M6812_OP_IDX) && !(mode & M6812_OP_D_IDX_2))
+ if (move_insn && !(val >= -16 && val <= 15)
+ && ((!(mode & M6812_OP_IDX) && !(mode & M6812_OP_D_IDX_2))
|| !(current_architecture & cpu9s12x)))
{
as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."),
f = m68hc11_new_insn (1);
number_to_chars_bigendian (f, opcode->opcode >> 8, 1); /* High byte. */
fixup8_xg (&operands[0].exp, format, M68XG_OP_REL9);
- }
+ }
else if (format & M68XG_OP_REL10)
{
f = m68hc11_new_insn (1);
}
else
as_bad ("No opcode found\n");
-
+
return;
}
else
{
opcode_local.opcode |= (operands[0].exp.X_add_number);
operands[0].mode = M68XG_OP_IMM3;
-
+
opcode = find (opc, operands, 1);
if (opcode)
{
if (opc->format & (M68XG_OP_REL9 | M68XG_OP_REL10))
{
- opcode_local.format = opc->format;
+ opcode_local.format = opc->format;
input_line_pointer = skip_whites (input_line_pointer);
expression (&operands[0].exp);
if (operands[0].exp.X_op == O_illegal)
if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r')
|| (*input_line_pointer == '\0'))
return; /* nothing left */
-
+
if (*input_line_pointer == '#')
{
as_bad ("No register specified before hash\n");
return;
- }
+ }
/* first operand is expected to be a register */
if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r'))
if (opcode)
opcode_local.opcode = opcode->opcode
| (operands[0].reg1 << 8);
-
+
if (operands[0].exp.X_op != O_constant)
as_bad ("Only constants supported at for IMM4 mode\n");
else
{
- if (check_range
+ if (check_range
(operands[0].exp.X_add_number,M68XG_OP_R_IMM4))
opcode_local.opcode
|= (operands[0].exp.X_add_number << 4);
com RD, RS alias for xnor RD,R0,RS
mov RD, RS alias for or RD, R0, RS
neg RD, RS alias for sub RD, R0, RS */
- opcode_local.opcode = opcode->opcode
+ opcode_local.opcode = opcode->opcode
| (operands[0].reg1 << 8) | (operands[1].reg1 << 2);
}
else if ((strncmp (opc->opcode->name, "cmp",3) == 0)
/* special cases for:
cmp RS1, RS2 alias for sub R0, RS1, RS2
cpc RS1, RS2 alias for sbc R0, RS1, RS2 */
- opcode_local.opcode = opcode->opcode
+ opcode_local.opcode = opcode->opcode
| (operands[0].reg1 << 5) | (operands[1].reg1 << 2);
}
else
opcode = find (opc, operands, 1);
if (opcode)
{
- opcode_local.opcode = opcode->opcode
+ opcode_local.opcode = opcode->opcode
| (operands[0].reg1 << 8) | (operands[1].reg1 << 5)
| (operands[2].reg1 << 2);
opcode_local.format = M68XG_OP_NONE;
}
input_line_pointer = skip_whites (input_line_pointer);
-
+
if (*input_line_pointer != ',')
{
as_bad (_("Missing operand."));
{
input_line_pointer++;
}
-
+
/* Ok so far, can only be one mode. */
opcode_local.format = M68XG_OP_R_R_OFFS5;
operands[0].mode = M68XG_OP_R_R_OFFS5;
value);
if (value >= 0)
where[0] |= value;
- else
+ else
where[0] |= (0x10 | (16 + value));
break;
/* sign bit already in xb postbyte */
if (value >= 0)
where[1] = value;
- else
+ else
where[1] = (256 + value);
break;
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0},
-
+
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
-
+
{mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
{mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
{mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0},
-
+
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
-
+
{mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
-
+
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
-
+
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
-
+
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0},
-
+
{mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
-
+
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
-
+
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
-
+
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
{mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1},
{mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
{mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
{mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
-
+
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
-
+
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
-
+
{fido_a, fido_ctrl, "fidoa", 0},
{fido_a, fido_ctrl, "fido", 1},
{ 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
{ 0, 0, 4, 0 },
{ 1, 1, 0, 0 },
-
+
{ 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
{ 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
{ 0, 0, 10, 0 },
else
{
const enum m68k_register *rp;
-
+
for (rp = control_regs; *rp; rp++)
{
if (*rp == opP->reg)
{
const struct m68k_cpu *alias;
int seen_master = 0;
-
+
if (any)
APPEND (", ");
any = 0;
{
int have_disp = 0;
int use_pl = 0;
-
+
/* This switch is a doozy.
Watch the first step; its a big one! */
switch (s[0])
case 'B':
tmpreg = get_num (&opP->disp, 90);
-
+
switch (s[1])
{
case 'B':
case 'g': /* Conditional branch */
have_disp = HAVE_LONG_CALL (current_architecture);
goto var_branch;
-
+
case 'b': /* Unconditional branch */
have_disp = HAVE_LONG_BRANCH (current_architecture);
use_pl = LONG_BRANCH_VIA_COND (current_architecture);
goto var_branch;
-
+
case 's': /* Unconditional subroutine */
have_disp = HAVE_LONG_CALL (current_architecture);
-
+
var_branch:
if (subs (&opP->disp) /* We can't relax it. */
#ifdef OBJ_ELF
as_warn (_("Can't use long branches on this architecture"));
goto long_branch;
}
-
+
/* This could either be a symbol, or an absolute
address. If it's an absolute address, turn it into
an absolute jump right here and keep it out of the
case 'e': /* EMAC ACCx, reg/reg. */
install_operand (s[1], opP->reg - ACC);
break;
-
+
case 'E': /* Ignore it. */
break;
}
if (!initialized)
m68k_init_arch ();
-
+
/* In MRI mode, the instruction and operands are separated by a
space. Anything following the operands is a comment. The label
has already been removed. */
slak->m_operands = ins->args;
slak->m_arch = ins->arch;
slak->m_opcode = ins->opcode;
-
+
/* In most cases we can determine the number of opcode words
by checking the second word of the mask. Unfortunately
some instructions have 2 opcode words, but no fixed bits
else
slak->m_codenum = 1;
slak->m_opnum = strlen (slak->m_operands) / 2;
-
+
if (i + 1 != m68k_numopcodes
&& !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
{
ignore_rest_of_line ();
return;
}
-
+
name = input_line_pointer;
while (*input_line_pointer && !ISSPACE(*input_line_pointer))
input_line_pointer++;
*input_line_pointer = 0;
m68k_set_cpu (name, 1, 0);
-
+
*input_line_pointer = saved_char;
demand_empty_rest_of_line ();
return;
ignore_rest_of_line ();
return;
}
-
+
name = input_line_pointer;
while (*input_line_pointer && *input_line_pointer != ','
&& !ISSPACE (*input_line_pointer))
}
while (m68k_set_extension (name, 1, 0));
}
-
+
*input_line_pointer = saved_char;
demand_empty_rest_of_line ();
return;
*negated = 1;
}
}
-
+
/* Remove 'm' or 'mc' prefix from 68k variants. */
if (allow_m)
{
}
else
current_architecture |= selected_cpu->arch;
-
+
current_architecture &= ~not_current_architecture;
if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
else
current_architecture &= ~m68k_mask;
}
-
+
/* Permit m68881 specification with all cpus; those that can't work
with a coprocessor could be doing emulation. */
if (current_architecture & m68851)
if (cpu_of_arch (current_architecture) < m68020
|| arch_coldfire_p (current_architecture))
md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
-
+
initialized = 1;
}
"), m68k_extensions[i].name,
m68k_extensions[i].alias > 0 ? " ColdFire"
: m68k_extensions[i].alias < 0 ? " m68k" : "");
-
+
fprintf (stream, _("\
-l use 1 word for refs to undefined symbols [default 2]\n\
-pic, -k generate position independent code\n\
--disp-size-default-16 displacement with unknown size is 16 bits\n\
--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
"));
-
+
fprintf (stream, _("Architecture variants are: "));
for (i = 0; m68k_archs[i].name; i++)
{
m68k_elf_final_processing (void)
{
unsigned flags = 0;
-
+
if (arch_coldfire_fpu (current_architecture))
flags |= EF_M68K_CFV4E;
/* Set file-specific flags if this is a cpu32 processor. */
else if ((cpu_of_arch (current_architecture) & m68000up)
&& !(cpu_of_arch (current_architecture) & m68020up))
flags |= EF_M68K_M68000;
-
+
if (current_architecture & mcfisa_a)
{
static const unsigned isa_features[][2] =
};
unsigned ix;
unsigned pattern;
-
+
pattern = (current_architecture
& (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
for (ix = 0; isa_features[ix][1]; ix++)
.align 2
0: .long disp
1:
-
+
If the b!cond is 4 byte aligned, the literal which would
go at x+4 will also be aligned. */
int first_inst = fragP->fr_fix + fragP->fr_address;
gas_cgen_initialize_saved_fixups_array();
}
-/* Variant of mep_cgen_assemble_insn. Assemble insn STR of cpu CD as a
+/* Variant of mep_cgen_assemble_insn. Assemble insn STR of cpu CD as a
coprocessor instruction, if possible, into FIELDS, BUF, and INSN. */
static const CGEN_INSN *
const char *errmsg = NULL;
/* The instructions are stored in hashed lists. */
- ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc,
+ ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc,
CGEN_INSN_MNEMONIC (pinsn));
start = str;
for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
{
const CGEN_INSN *insn = ilist->insn;
- if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn),
+ if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn),
CGEN_INSN_MNEMONIC (pinsn)) == 0
&& MEP_INSN_COP_P (ilist->insn)
&& mep_cgen_insn_supported (cd, insn))
errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
if (errmsg != NULL)
continue;
-
+
errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
(bfd_vma) 0);
if (errmsg != NULL)
as_bad (_("core and copro insn lengths must total 32 bits."));
}
else
- as_bad (_("vliw group must consist of 1 core and 1 copro insn."));
+ as_bad (_("vliw group must consist of 1 core and 1 copro insn."));
}
else
{
CGEN_INSN_VLIW32_NO_MATCHING_NOP))
as_fatal ("No valid nop.");
- /* At this point we know that we have a single 16-bit insn that has
- a matching nop. We have to assemble it and put it into the saved
+ /* At this point we know that we have a single 16-bit insn that has
+ a matching nop. We have to assemble it and put it into the saved
insn and fixup chain arrays. */
if (insn0iscopro)
{
char *errmsg;
mep_insn insn;
-
+
/* Move the insn and it's fixups to the second element of the
saved insns arrary and insert a 16 bit core nope into the
first element. */
/* Move the insn in element 0 to element 1 and insert the
nop into element 0. Move the fixups in element 0 to
- element 1 and save the current fixups to element 0.
+ element 1 and save the current fixups to element 0.
Really there aren't any fixups at this point because we're
inserting a nop but we might as well be general so that
if there's ever a need to insert a general insn, we'll
nop has been added, then make the necessary changes and
handle its assembly and insertion here. Otherwise,
go figure out why either:
-
+
1. The assembler thinks that there is a 32-bit core nop
to match a 32-bit coprocessor insn, or
2. The assembler thinks that there is a 48-bit core nop
/* Move the insn in element 0 to element 1 and insert the
nop into element 0. Move the fixups in element 0 to
- element 1 and save the current fixups to element 0.
+ element 1 and save the current fixups to element 0.
Really there aren't any fixups at this point because we're
inserting a nop but we might as well be general so that
if there's ever a need to insert a general insn, we'll
mep_check_parallel_scheduling (void)
{
/* This is where we will eventually read the config information
- and choose which scheduling checking function to call. */
+ and choose which scheduling checking function to call. */
#ifdef MEP_IVC2_SUPPORTED
if (mep_cop == EF_MEP_COP_IVC2)
mep_check_ivc2_scheduling ();
int thisInsnIsCopro = 0;
mep_insn insn;
int i;
-
+
/* Initialize the insn buffer */
-
+
if (! CGEN_INT_INSN_P)
for (i=0; i < CGEN_MAX_INSN_SIZE; i++)
insn.buffer[i]='\0';
switch (fragP->fr_cgen.insn->base->num)
{
case MEP_INSN_BSR12:
- fragP->fr_subtype = insn_to_subtype
+ fragP->fr_subtype = insn_to_subtype
(subtype_mappings[fragP->fr_subtype].insn_for_extern);
break;
case MEP_INSN_BEQZ:
}
void
-md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
segT seg ATTRIBUTE_UNUSED,
fragS *fragP)
{
#ifdef OBJ_COMPLEX_RELC
/* coalescing this into RELOC_MEP_16 is actually a bug,
since it's a signed operand. let the relc code handle it. */
- return BFD_RELOC_RELC;
+ return BFD_RELOC_RELC;
#endif
case MEP_OPERAND_UIMM16:
default:
#ifdef OBJ_COMPLEX_RELC
- /* this is not an error, yet.
+ /* this is not an error, yet.
pass it to the linker. */
return BFD_RELOC_RELC;
#endif
pluspresent = 0;
}
- return 1;
+ return 1;
}
#define ELF_TC_SPECIAL_SECTIONS \
{ VTEXT_SECTION_NAME, SHT_PROGBITS, SHF_ALLOC|SHF_EXECINSTR|SHF_MEP_VLIW },
-/* The values of the following enum are for use with parinsnum, which
+/* The values of the following enum are for use with parinsnum, which
is a variable in md_assemble that keeps track of whether or not the
next instruction is expected to be the first or second instrucion in
a parallelization group. */
/* We want local label support. */
#define LOCAL_LABELS_FB 1
-
+
/* Want the section information too... */
#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
#endif
#include "write.h" /* For definition of fixS */
-
+
extern void md_begin (void);
extern void md_assemble (char *);
extern symbolS * md_undefined_symbol (char *);
{
for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
;
-
+
si = seg_info (now_seg);
*pl = si->label_list;
si->label_list = NULL;
{"$28", RTYPE_NUM | 28}, \
{"$29", RTYPE_NUM | 29}, \
{"$30", RTYPE_NUM | 30}, \
- {"$31", RTYPE_NUM | 31}
+ {"$31", RTYPE_NUM | 31}
#define FPU_REGISTER_NAMES \
{"$f0", RTYPE_FPU | 0}, \
{"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
{"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
{"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
- {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
+ {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
/* Remaining symbolic register names */
#define SYMBOLIC_REGISTER_NAMES \
/* The $txx registers depends on the abi,
these will be added later into the symbol table from
- one of the tables below once mips_abi is set after
+ one of the tables below once mips_abi is set after
parsing of arguments from the command line. */
SYMBOLIC_REGISTER_NAMES,
/* We add all the general register names to the symbol table. This
helps us detect invalid uses of them. */
- for (i = 0; reg_names[i].name; i++)
+ for (i = 0; reg_names[i].name; i++)
symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
reg_names[i].num, /* & RNUM_MASK, */
&zero_address_frag));
if (HAVE_NEWABI)
- for (i = 0; reg_names_n32n64[i].name; i++)
+ for (i = 0; reg_names_n32n64[i].name; i++)
symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
reg_names_n32n64[i].num, /* & RNUM_MASK, */
&zero_address_frag));
else
- for (i = 0; reg_names_o32[i].name; i++)
+ for (i = 0; reg_names_o32[i].name; i++)
symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
reg_names_o32[i].num, /* & RNUM_MASK, */
&zero_address_frag));
* Run the data cache in write-through mode.
* Insert a non-store instruction between
Store A and Store B or Store B and Store C. */
-
+
static int
nops_for_24k (int ignore, const struct mips_cl_insn *hist,
const struct mips_cl_insn *insn)
abort ();
break;
-
+
case M_SAA_AB:
s = "saa";
goto saa_saad;
{ "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
/* Broadcom SB-1A CPU core */
{ "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
-
+
{ "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A },
/* MIPS 64 Release 2 */
-mno-micromips do not generate microMIPS instructions\n"));
fprintf (stream, _("\
-msmartmips generate smartmips instructions\n\
--mno-smartmips do not generate smartmips instructions\n"));
+-mno-smartmips do not generate smartmips instructions\n"));
fprintf (stream, _("\
-mdsp generate DSP instructions\n\
-mno-dsp do not generate DSP instructions\n"));
if (*s == 0 || is_end_of_line[(unsigned int) *s])
/* We avoid handling empty lines here. */
return;
-
+
if (is_name_beginner (*s))
label = s;
fragP->fr_subtype = ENCODE_RELAX (STATE_PUSHJSTUB, STATE_ZERO);
}
/* FALLTHROUGH. */
-
+
/* See if this PUSHJ is redirectable to a stub. */
case ENCODE_RELAX (STATE_PUSHJSTUB, STATE_ZERO):
{
as_warn (_("could not set architecture and machine"));
current_machine = AM33_2;
-#else
+#else
if (!bfd_set_arch_mach (stdoutput, bfd_arch_mn10300, MN103))
as_warn (_("could not set architecture and machine"));
as_bad (_("unsupported BFD relocation size %u"), size);
fixup.reloc = BFD_RELOC_UNUSED;
}
-
+
fix_new_exp (frag, off, size, &fixup.exp, 0, fixup.reloc);
}
reloc2->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
*reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy);
- reloc->addend = fixp->fx_offset;
+ reloc->addend = fixp->fx_offset;
if (asec == absolute_section)
{
reloc->addend += S_GET_VALUE (fixp->fx_addsy);
has_known_symbol_location (fragS * fragp, asection * sec)
{
symbolS * sym = fragp->fr_symbol;
-
+
return sym != NULL
&& S_IS_DEFINED (sym)
&& ! S_IS_WEAK (sym)
case BFD_RELOC_MN10300_ALIGN:
fixP->fx_done = 1;
return;
-
+
case BFD_RELOC_NONE:
default:
as_bad_where (fixP->fx_file, fixP->fx_line,
return cont + len;
return NULL;
-}
+}
int
mn10300_parse_name (char const *name,
}
exprP->X_add_symbol = symbol_find_or_make (name);
-
+
if (*nextcharP != '@')
goto no_suffix;
else if ((next_end = mn10300_end_of_match (next + 1, "GOTOFF")))
{
switch (c)
{
- case OPTION_EB:
- target_big_endian = 1;
+ case OPTION_EB:
+ target_big_endian = 1;
break;
- case OPTION_EL:
+ case OPTION_EL:
target_big_endian = 0;
break;
- default:
+ default:
return 0;
}
/* Apply a fixup to the object file. */
void
-md_apply_fix (fixS *fixP ATTRIBUTE_UNUSED,
+md_apply_fix (fixS *fixP ATTRIBUTE_UNUSED,
valueT * valP ATTRIBUTE_UNUSED, segT seg ATTRIBUTE_UNUSED)
{
char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
support the 430 ISA. */
static const char * msp430_mcu_names [] =
{
-"msp430afe221", "msp430afe222", "msp430afe223", "msp430afe231",
-"msp430afe232", "msp430afe233", "msp430afe251", "msp430afe252",
-"msp430afe253", "msp430c091", "msp430c092", "msp430c111",
-"msp430c1111", "msp430c112", "msp430c1121", "msp430c1331",
-"msp430c1351", "msp430c311s", "msp430c312", "msp430c313",
-"msp430c314", "msp430c315", "msp430c323", "msp430c325",
-"msp430c336", "msp430c337", "msp430c412", "msp430c413",
-"msp430e112", "msp430e313", "msp430e315", "msp430e325",
-"msp430e337", "msp430f110", "msp430f1101", "msp430f1101a",
-"msp430f1111", "msp430f1111a", "msp430f112", "msp430f1121",
-"msp430f1121a", "msp430f1122", "msp430f1132", "msp430f122",
-"msp430f1222", "msp430f123", "msp430f1232", "msp430f133",
-"msp430f135", "msp430f147", "msp430f1471", "msp430f148",
-"msp430f1481", "msp430f149", "msp430f1491", "msp430f155",
-"msp430f156", "msp430f157", "msp430f1610", "msp430f1611",
-"msp430f1612", "msp430f167", "msp430f168", "msp430f169",
-"msp430f2001", "msp430f2002", "msp430f2003", "msp430f2011",
-"msp430f2012", "msp430f2013", "msp430f2101", "msp430f2111",
-"msp430f2112", "msp430f2121", "msp430f2122", "msp430f2131",
-"msp430f2132", "msp430f2232", "msp430f2234", "msp430f2252",
-"msp430f2254", "msp430f2272", "msp430f2274", "msp430f233",
-"msp430f2330", "msp430f235", "msp430f2350", "msp430f2370",
-"msp430f2410", "msp430f247", "msp430f2471", "msp430f248",
-"msp430f2481", "msp430f249", "msp430f2491", "msp430f412",
-"msp430f413", "msp430f4132", "msp430f415", "msp430f4152",
-"msp430f417", "msp430f423", "msp430f423a", "msp430f425",
-"msp430f4250", "msp430f425a", "msp430f4260", "msp430f427",
-"msp430f4270", "msp430f427a", "msp430f435", "msp430f4351",
-"msp430f436", "msp430f4361", "msp430f437", "msp430f4371",
-"msp430f438", "msp430f439", "msp430f447", "msp430f448",
-"msp430f4481", "msp430f449", "msp430f4491", "msp430f477",
-"msp430f478", "msp430f4783", "msp430f4784", "msp430f479",
-"msp430f4793", "msp430f4794", "msp430fe423", "msp430fe4232",
-"msp430fe423a", "msp430fe4242", "msp430fe425", "msp430fe4252",
-"msp430fe425a", "msp430fe427", "msp430fe4272", "msp430fe427a",
-"msp430fg4250", "msp430fg4260", "msp430fg4270", "msp430fg437",
-"msp430fg438", "msp430fg439", "msp430fg477", "msp430fg478",
-"msp430fg479", "msp430fw423", "msp430fw425", "msp430fw427",
-"msp430fw428", "msp430fw429", "msp430g2001", "msp430g2101",
-"msp430g2102", "msp430g2111", "msp430g2112", "msp430g2113",
-"msp430g2121", "msp430g2131", "msp430g2132", "msp430g2152",
-"msp430g2153", "msp430g2201", "msp430g2202", "msp430g2203",
-"msp430g2210", "msp430g2211", "msp430g2212", "msp430g2213",
-"msp430g2221", "msp430g2230", "msp430g2231", "msp430g2232",
-"msp430g2233", "msp430g2252", "msp430g2253", "msp430g2302",
-"msp430g2303", "msp430g2312", "msp430g2313", "msp430g2332",
-"msp430g2333", "msp430g2352", "msp430g2353", "msp430g2402",
-"msp430g2403", "msp430g2412", "msp430g2413", "msp430g2432",
-"msp430g2433", "msp430g2444", "msp430g2452", "msp430g2453",
-"msp430g2513", "msp430g2533", "msp430g2544", "msp430g2553",
-"msp430g2744", "msp430g2755", "msp430g2855", "msp430g2955",
-"msp430i2020", "msp430i2021", "msp430i2030", "msp430i2031",
-"msp430i2040", "msp430i2041", "msp430l092", "msp430p112",
-"msp430p313", "msp430p315", "msp430p315s", "msp430p325",
+"msp430afe221", "msp430afe222", "msp430afe223", "msp430afe231",
+"msp430afe232", "msp430afe233", "msp430afe251", "msp430afe252",
+"msp430afe253", "msp430c091", "msp430c092", "msp430c111",
+"msp430c1111", "msp430c112", "msp430c1121", "msp430c1331",
+"msp430c1351", "msp430c311s", "msp430c312", "msp430c313",
+"msp430c314", "msp430c315", "msp430c323", "msp430c325",
+"msp430c336", "msp430c337", "msp430c412", "msp430c413",
+"msp430e112", "msp430e313", "msp430e315", "msp430e325",
+"msp430e337", "msp430f110", "msp430f1101", "msp430f1101a",
+"msp430f1111", "msp430f1111a", "msp430f112", "msp430f1121",
+"msp430f1121a", "msp430f1122", "msp430f1132", "msp430f122",
+"msp430f1222", "msp430f123", "msp430f1232", "msp430f133",
+"msp430f135", "msp430f147", "msp430f1471", "msp430f148",
+"msp430f1481", "msp430f149", "msp430f1491", "msp430f155",
+"msp430f156", "msp430f157", "msp430f1610", "msp430f1611",
+"msp430f1612", "msp430f167", "msp430f168", "msp430f169",
+"msp430f2001", "msp430f2002", "msp430f2003", "msp430f2011",
+"msp430f2012", "msp430f2013", "msp430f2101", "msp430f2111",
+"msp430f2112", "msp430f2121", "msp430f2122", "msp430f2131",
+"msp430f2132", "msp430f2232", "msp430f2234", "msp430f2252",
+"msp430f2254", "msp430f2272", "msp430f2274", "msp430f233",
+"msp430f2330", "msp430f235", "msp430f2350", "msp430f2370",
+"msp430f2410", "msp430f247", "msp430f2471", "msp430f248",
+"msp430f2481", "msp430f249", "msp430f2491", "msp430f412",
+"msp430f413", "msp430f4132", "msp430f415", "msp430f4152",
+"msp430f417", "msp430f423", "msp430f423a", "msp430f425",
+"msp430f4250", "msp430f425a", "msp430f4260", "msp430f427",
+"msp430f4270", "msp430f427a", "msp430f435", "msp430f4351",
+"msp430f436", "msp430f4361", "msp430f437", "msp430f4371",
+"msp430f438", "msp430f439", "msp430f447", "msp430f448",
+"msp430f4481", "msp430f449", "msp430f4491", "msp430f477",
+"msp430f478", "msp430f4783", "msp430f4784", "msp430f479",
+"msp430f4793", "msp430f4794", "msp430fe423", "msp430fe4232",
+"msp430fe423a", "msp430fe4242", "msp430fe425", "msp430fe4252",
+"msp430fe425a", "msp430fe427", "msp430fe4272", "msp430fe427a",
+"msp430fg4250", "msp430fg4260", "msp430fg4270", "msp430fg437",
+"msp430fg438", "msp430fg439", "msp430fg477", "msp430fg478",
+"msp430fg479", "msp430fw423", "msp430fw425", "msp430fw427",
+"msp430fw428", "msp430fw429", "msp430g2001", "msp430g2101",
+"msp430g2102", "msp430g2111", "msp430g2112", "msp430g2113",
+"msp430g2121", "msp430g2131", "msp430g2132", "msp430g2152",
+"msp430g2153", "msp430g2201", "msp430g2202", "msp430g2203",
+"msp430g2210", "msp430g2211", "msp430g2212", "msp430g2213",
+"msp430g2221", "msp430g2230", "msp430g2231", "msp430g2232",
+"msp430g2233", "msp430g2252", "msp430g2253", "msp430g2302",
+"msp430g2303", "msp430g2312", "msp430g2313", "msp430g2332",
+"msp430g2333", "msp430g2352", "msp430g2353", "msp430g2402",
+"msp430g2403", "msp430g2412", "msp430g2413", "msp430g2432",
+"msp430g2433", "msp430g2444", "msp430g2452", "msp430g2453",
+"msp430g2513", "msp430g2533", "msp430g2544", "msp430g2553",
+"msp430g2744", "msp430g2755", "msp430g2855", "msp430g2955",
+"msp430i2020", "msp430i2021", "msp430i2030", "msp430i2031",
+"msp430i2040", "msp430i2041", "msp430l092", "msp430p112",
+"msp430p313", "msp430p315", "msp430p315s", "msp430p325",
"msp430p337", "msp430tch5e"
};
char * name = obj_elf_section_name ();
msp430_make_init_symbols (name);
-
+
input_line_pointer = saved_ilp;
obj_elf_section (arg);
}
opcode->name);
return 0;
}
-
+
fmt = (-fmt) - 1;
extended_op = TRUE;
}
as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
break;
}
-
+
line = extract_operand (line, l1, sizeof (l1));
if (l1[0])
{
value &= 0xffff; /* Get rid of extended sign. */
bfd_putl16 ((bfd_vma) value, where);
break;
-
+
case BFD_RELOC_32:
bfd_putl16 ((bfd_vma) value, where);
break;
#include "as.h"
#include "dwarf2dbg.h"
-#include "subsegs.h"
+#include "subsegs.h"
#include "symcat.h"
#include "opcodes/mt-desc.h"
#include "opcodes/mt-opc.h"
const char comment_chars[] = ";";
const char line_comment_chars[] = "#";
-const char line_separator_chars[] = "";
+const char line_separator_chars[] = "";
const char EXP_CHARS[] = "eE";
const char FLT_CHARS[] = "dD";
/* The target specific pseudo-ops which we support. */
const pseudo_typeS md_pseudo_table[] =
{
- { "word", cons, 4 },
+ { "word", cons, 4 },
{ NULL, NULL, 0 }
};
static int no_scheduling_restrictions = 0;
-struct option md_longopts[] =
+struct option md_longopts[] =
{
#define OPTION_NO_SCHED_REST (OPTION_MD_BASE)
{ "nosched", no_argument, NULL, OPTION_NO_SCHED_REST },
md_begin (void)
{
/* Initialize the `cgen' interface. */
-
+
/* Set the machine number and endian. */
gas_cgen_cpu_desc = mt_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, mt_mach_bitmask,
CGEN_CPU_OPEN_ENDIAN,
as_warn (_("operand references R%ld of instruction before previous."),
prev_delayed_load_register);
}
-
+
/* Detect data dependency between conditional branch instruction
and an immediately preceding arithmetic or logical instruction. */
if (last_insn_was_arithmetic_or_logic
last_insn_was_branch_insn =
CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN);
-
+
last_insn_was_conditional_branch_insn =
CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN)
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2);
-
+
prev_delayed_load_register = delayed_load_register;
-
+
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDR))
- delayed_load_register = insn.fields.f_dr;
+ delayed_load_register = insn.fields.f_dr;
else if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDRRR))
- delayed_load_register = insn.fields.f_drrr;
+ delayed_load_register = insn.fields.f_drrr;
else /* Insns has no destination register. */
- delayed_load_register = 0;
+ delayed_load_register = 0;
/* Generate dwarf2 line numbers. */
- dwarf2_emit_insn (4);
+ dwarf2_emit_insn (4);
}
valueT
{
as_fatal (_("md_estimate_size_before_relax\n"));
return 1;
-}
+}
/* *fragP has been relaxed to its final size, and now needs to have
the bytes inside it modified to conform to the new size.
if (fixP->fx_addsy == NULL)
return TRUE;
-
+
/* Prevent all adjustments to global symbols. */
if (S_IS_EXTERNAL (fixP->fx_addsy))
return FALSE;
-
+
if (S_IS_WEAK (fixP->fx_addsy))
return FALSE;
-
+
return 1;
}
#define LITERAL_PREFIXPERCENT_BIN
#define md_apply_fix mt_apply_fix
-extern void mt_apply_fix (struct fix *, valueT *, segT);
+extern void mt_apply_fix (struct fix *, valueT *, segT);
/* Call md_pcrel_from_section(), not md_pcrel_from(). */
#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
do not generate warnings. */
bfd_boolean noat;
- /* .set nobreak -> nobreak = 1 allows assembly code to use ba,bt without
+ /* .set nobreak -> nobreak = 1 allows assembly code to use ba,bt without
warning.
.set break -> nobreak = 0, assembly code using ba,bt warns. */
bfd_boolean nobreak;
/* Constant bits masked into insn_code for self-check mode. */
unsigned long constant_bits;
-
+
/* Pointer to the relevant bit of the opcode table. */
const struct nios2_opcode *insn_nios2_opcode;
/* After parsing ptrs to the tokens in the instruction fill this array
trying a directive. This prevents
us from polluting the name space. */
SKIP_WHITESPACE ();
- if (is_end_of_line[(unsigned char) *input_line_pointer])
+ if (is_end_of_line[(unsigned char) *input_line_pointer])
{
bfd_boolean done = TRUE;
*endline = 0;
-
+
if (!strcmp (directive, "noat"))
nios2_as_options.noat = TRUE;
else if (!strcmp (directive, "at"))
nios2_as_options.relax = relax_all;
else
done = FALSE;
-
+
if (done)
{
*endline = delim;
}
/* If we fall through to here, either we have ".set XXX, YYY"
- or we have ".set XXX" where XXX is unknown or we have
+ or we have ".set XXX" where XXX is unknown or we have
a syntax error. */
input_line_pointer = directive;
*endline = delim;
Nios II PC-relative branch instructions only support 16-bit offsets.
And, there's no good way to add a 32-bit constant to the PC without
using two registers.
-
+
To deal with this, for the pc-relative relaxation mode we convert
br label
into a series of 16-bit adds, like:
16-bit CDX branch instructions are relaxed first into equivalent
32-bit branches and then the above transformations are applied
- if necessary.
+ if necessary.
*/
md_number_to_chars (buffer, op, 4);
fragp->fr_fix += 4;
buffer += 4;
-
+
/* We need to know whether the offset is positive or negative. */
target += S_GET_VALUE (symbolp);
offset = target - fragp->fr_address - fragp->fr_fix;
= ((fixP->fx_frag->fr_address + fixP->fx_where) & 0xf0000000);
range_max = range_min + 0x0fffffff;
address = fixup | range_min;
-
+
as_bad_where (fixP->fx_file, fixP->fx_line,
_("call target address 0x%08x out of range 0x%08x to 0x%08x"),
address, range_min, range_max);
if (fixP->fx_r_type == BFD_RELOC_64)
{
/* We may reach here due to .8byte directives, but we never output
- BFD_RELOC_64; it must be resolved. */
+ BFD_RELOC_64; it must be resolved. */
if (fixP->fx_addsy != NULL)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("cannot create 64-bit relocation"));
/* The various nios2_assemble_* functions call this
function to generate an expression from a string representing an expression.
It then tries to evaluate the expression, and if it can, returns its value.
- If not, it creates a new nios2_insn_relocS and stores the expression and
+ If not, it creates a new nios2_insn_relocS and stores the expression and
reloc_type for future use. */
static unsigned long
nios2_assemble_expression (const char *exprstr,
{
reloc_type = nios2_special_reloc[i].reloc_type;
exprstr += strlen (nios2_special_reloc[i].string) + 1;
-
+
/* %lo and %hiadj have different meanings for PC-relative
expressions. */
if (pcrel)
if (reloc_type == BFD_RELOC_NIOS2_HIADJ16)
reloc_type = BFD_RELOC_NIOS2_PCREL_HA;
}
-
+
break;
}
/* Control register index. */
-static void
+static void
nios2_assemble_arg_c (const char *token, nios2_insn_infoS *insn)
{
struct nios2_reg *reg = nios2_parse_reg (token, REG_CONTROL);
}
/* Destination register. */
-static void
+static void
nios2_assemble_arg_d (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* Source register 1. */
-static void
+static void
nios2_assemble_arg_s (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* Source register 2. */
-static void
+static void
nios2_assemble_arg_t (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* Destination register w/3-bit encoding. */
-static void
+static void
nios2_assemble_arg_D (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
int reg = nios2_assemble_reg3 (token);
-
+
switch (op->format)
{
case iw_T1I7_type:
}
/* Source register w/3-bit encoding. */
-static void
+static void
nios2_assemble_arg_S (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
int reg = nios2_assemble_reg3 (token);
-
+
switch (op->format)
{
case iw_T1I7_type:
}
/* Source register 2 w/3-bit encoding. */
-static void
+static void
nios2_assemble_arg_T (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
int reg = nios2_assemble_reg3 (token);
-
+
switch (op->format)
{
case iw_T2I4_type:
}
/* 16-bit signed immediate. */
-static void
+static void
nios2_assemble_arg_i (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* 12-bit signed immediate. */
-static void
+static void
nios2_assemble_arg_I (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* 16-bit unsigned immediate. */
-static void
+static void
nios2_assemble_arg_u (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* 7-bit unsigned immediate with 2-bit shift. */
-static void
+static void
nios2_assemble_arg_U (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* 5-bit unsigned immediate with 2-bit shift. */
-static void
+static void
nios2_assemble_arg_V (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* 4-bit unsigned immediate with 2-bit shift. */
-static void
+static void
nios2_assemble_arg_W (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
insn->constant_bits |= SET_IW_T2I4_IMM4 (val >> 2);
break;
case iw_L5I4X1_type:
- /* This argument is optional for push.n/pop.n, and defaults to
+ /* This argument is optional for push.n/pop.n, and defaults to
zero if unspecified. */
if (token == NULL)
return;
}
/* 4-bit unsigned immediate with 1-bit shift. */
-static void
+static void
nios2_assemble_arg_X (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* 4-bit unsigned immediate without shift. */
-static void
+static void
nios2_assemble_arg_Y (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
/* 16-bit signed immediate address offset. */
-static void
+static void
nios2_assemble_arg_o (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* 10-bit signed address offset with 1-bit shift. */
-static void
+static void
nios2_assemble_arg_O (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* 7-bit signed address offset with 1-bit shift. */
-static void
+static void
nios2_assemble_arg_P (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* 5-bit unsigned immediate. */
-static void
+static void
nios2_assemble_arg_j (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* Second 5-bit unsigned immediate field. */
-static void
+static void
nios2_assemble_arg_k (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* 8-bit unsigned immediate. */
-static void
+static void
nios2_assemble_arg_l (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* 26-bit unsigned immediate. */
-static void
+static void
nios2_assemble_arg_m (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* 6-bit unsigned immediate with no shifting. */
-static void
+static void
nios2_assemble_arg_M (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* 6-bit unsigned immediate with 2-bit shift. */
-static void
+static void
nios2_assemble_arg_N (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
/* Encoded enumeration for addi.n/subi.n. */
-static void
+static void
nios2_assemble_arg_e (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* Encoded enumeration for slli.n/srli.n. */
-static void
+static void
nios2_assemble_arg_f (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* Encoded enumeration for andi.n. */
-static void
+static void
nios2_assemble_arg_g (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* Encoded enumeration for movi.n. */
-static void
+static void
nios2_assemble_arg_h (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
}
/* Encoded REGMASK for ldwm/stwm or push.n/pop.n. */
-static void
+static void
nios2_assemble_arg_R (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
insn->insn_code |= SET_IW_L5I4X1_CS (1);
}
break;
-
+
default:
bad_opcode (op);
}
}
/* Base register for ldwm/stwm. */
-static void
+static void
nios2_assemble_arg_B (const char *token, nios2_insn_infoS *insn)
{
const struct nios2_opcode *op = insn->insn_nios2_opcode;
switch (op->format)
{
case iw_F1X4L17_type:
- /* For ldwm, check to see if the base register is already inside the
+ /* For ldwm, check to see if the base register is already inside the
register list. */
if (op->match == MATCH_R2_LDWM
&& (nios2_reglist_mask & (1 << reg->index)))
case 'c':
nios2_assemble_arg_c (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'd':
nios2_assemble_arg_d (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 's':
nios2_assemble_arg_s (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 't':
nios2_assemble_arg_t (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'D':
nios2_assemble_arg_D (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'S':
nios2_assemble_arg_S (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'T':
nios2_assemble_arg_T (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'i':
nios2_assemble_arg_i (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'I':
nios2_assemble_arg_I (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'u':
nios2_assemble_arg_u (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'U':
nios2_assemble_arg_U (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'V':
nios2_assemble_arg_V (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'W':
nios2_assemble_arg_W (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'X':
nios2_assemble_arg_X (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'Y':
nios2_assemble_arg_Y (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'o':
nios2_assemble_arg_o (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'O':
nios2_assemble_arg_O (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'P':
nios2_assemble_arg_P (insn->insn_tokens[tokidx++], insn);
break;
case 'j':
nios2_assemble_arg_j (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'k':
nios2_assemble_arg_k (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'l':
nios2_assemble_arg_l (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'm':
nios2_assemble_arg_m (insn->insn_tokens[tokidx++], insn);
break;
case 'e':
nios2_assemble_arg_e (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'f':
nios2_assemble_arg_f (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'g':
nios2_assemble_arg_g (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'h':
nios2_assemble_arg_h (insn->insn_tokens[tokidx++], insn);
break;
-
+
case 'R':
nios2_assemble_arg_R (insn->insn_tokens[tokidx++], insn);
break;
break;
}
- /* Perform argument checking. */
+ /* Perform argument checking. */
nios2_check_assembly (insn->insn_code | insn->constant_bits,
insn->insn_tokens[tokidx]);
}
nios2_consume_arg (char *argstr, const char *parsestr)
{
char *temp;
-
+
switch (*parsestr)
{
case 'c':
case 'h':
case 'M':
case 'N':
-
+
/* We can't have %hi, %lo or %hiadj here. */
if (*argstr == '%')
as_bad (_("badly formed expression near %s"), argstr);
p = argstr;
i = 0;
bfd_boolean terminate = FALSE;
-
+
/* This rest of this function is it too fragile and it mostly works,
therefore special case this one. */
if (*parsestr == 0 && argstr != 0)
parsed_args[0] = NULL;
return;
}
-
+
while (p != NULL && !terminate && i < NIOS2_MAX_INSN_TOKENS)
{
parsed_args[i] = nios2_consume_arg (p, parsestr);
parsed_args[i + 1] = NULL;
}
-/* This function inserts the string insert num times in the array
+/* This function inserts the string insert num times in the array
parsed_args, starting at the index start. */
static void
nios2_insert_arg (char **parsed_args, const char *insert, int num,
output_insn (nios2_insn_infoS *insn)
{
char *f;
- nios2_insn_relocS *reloc;
+ nios2_insn_relocS *reloc;
f = frag_more (insn->insn_nios2_opcode->size);
/* This allocates enough space for the instruction
and puts it in the current frag. */
break;
}
- /* Create and fill a hashtable for the Nios II opcodes, registers and
+ /* Create and fill a hashtable for the Nios II opcodes, registers and
arguments. */
nios2_opcode_hash = hash_new ();
nios2_reg_hash = hash_new ();
void
md_assemble (char *op_str)
{
- char *argstr;
+ char *argstr;
char *op_strdup = NULL;
unsigned long saved_pinfo = 0;
nios2_insn_infoS thisinsn;
nios2_parse_args (insn, argstr, insn->insn_nios2_opcode->args_test,
(char **) &insn->insn_tokens[1]);
- /* We need to preserve the MOVIA macro as this is clobbered by
+ /* We need to preserve the MOVIA macro as this is clobbered by
translate_pseudo_insn. */
if (insn->insn_nios2_opcode->pinfo == NIOS2_INSN_MACRO_MOVIA)
saved_pinfo = NIOS2_INSN_MACRO_MOVIA;
- /* If the instruction is an pseudo-instruction, we want to replace it
+ /* If the instruction is an pseudo-instruction, we want to replace it
with its real equivalent, and then continue. */
if ((insn->insn_nios2_opcode->pinfo & NIOS2_INSN_MACRO)
== NIOS2_INSN_MACRO)
addrmodeP->am_size += 1;
}
- gas_assert (addrmodeP->mode >= 0);
+ gas_assert (addrmodeP->mode >= 0);
if (disp_test[(unsigned int) addrmodeP->mode])
{
char c;
if (opcode->flags & PPC_OPCODE_VLE)
{
int tmp_insn = insn & opcode->mask;
-
+
int use_d_reloc = (tmp_insn == E_OR2I_INSN
|| tmp_insn == E_AND2I_DOT_INSN
|| tmp_insn == E_OR2IS_INSN
else if (use_a_reloc)
reloc = BFD_RELOC_PPC_VLE_HI16A;
break;
-
+
case BFD_RELOC_HI16_S:
if (use_d_reloc)
reloc = BFD_RELOC_PPC_VLE_HA16D;
fprintf(stderr, "Missed case %d %d at 0x%lx\n",
rl78_opcode_type (fragP->fr_opcode), fragP->fr_subtype, mypc);
abort ();
-
+
}
break;
the __rl78_abs__ symbol and arrange for the linker scripts to place
this symbol at address 0. */
#define OPIMM(IMM) OPX (BFD_RELOC_RL78_SYM, symbol_get_bfdsym (rl78_abs_sym), IMM)
-
+
#define OP(OP) OPX(BFD_RELOC_RL78_##OP, *reloc[0]->sym_ptr_ptr, 0)
#define SYM0() reloc[0]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RL78_SYM)
}
else if (sec)
is_opcode = sec->flags & SEC_CODE;
-
+
/* Certain BFD relocations cannot be translated directly into
a single (non-Red Hat) RX relocation, but instead need
multiple RX relocations - handle them here. */
mop |= (unsigned int) ((value & 0xfff) << 8 |
(value & 0xff000) >> 12);
bfd_putb32 ((bfd_vma) mop, (unsigned char *) where);
- }
+ }
break;
case BFD_RELOC_16:
/* tc-score.h -- Score specific file for assembler
Copyright (C) 2006-2015 Free Software Foundation, Inc.
- Contributed by:
+ Contributed by:
Brain.lin (brain.lin@sunplusct.com)
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
-
+
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
}
else
prefix = 0;
-
+
consumed = parse_reg_without_prefix (src, mode, reg);
if (consumed == 0)
for (; bfd_arch; bfd_arch=bfd_arch->next)
{
int len = strlen(bfd_arch->printable_name);
-
+
if (bfd_arch->mach == bfd_mach_sh5)
continue;
-
+
if (strncasecmp (bfd_arch->printable_name, arg, len) != 0)
continue;
continue;
break;
}
-
+
if (!preset_target_arch)
as_bad (_("Invalid argument to --isa option: %s"), arg);
}
{ "v8pluse", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VE, 0 },
{ "v8plusv", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VV, 0 },
{ "v8plusm", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VM, 0 },
-
+
{ "v9", "v9", v9, 0, 1, HWS_V9, 0 },
{ "v9a", "v9a", v9, 0, 1, HWS_VA, 0 },
{ "v9b", "v9b", v9, 0, 1, HWS_VB, 0 },
#include "as.h"
#include "safe-ctype.h"
#include "subsegs.h"
-#include "dwarf2dbg.h"
+#include "dwarf2dbg.h"
const struct spu_opcode spu_opcodes[] = {
#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
{
int arg = format->arg[i];
char *exp;
- if (i > 1 && arg != A_P && format->arg[i-1] != A_P)
+ if (i > 1 && arg != A_P && format->arg[i-1] != A_P)
buf[len++] = ',';
if (arg == A_P)
exp = "(";
else if (arg < A_P)
exp = i == syntax_error_arg ? "REG" : "reg";
- else
+ else
exp = i == syntax_error_arg ? "IMM" : "imm";
len += sprintf (&buf[len], "%s", exp);
- if (i > 1 && format->arg[i-1] == A_P)
+ if (i > 1 && format->arg[i-1] == A_P)
buf[len++] = ')';
}
buf[len] = 0;
/* if this instruction requires labels mark it for later */
for (i = 0; i < MAX_RELOCS; i++)
- if (insn.reloc_arg[i] >= 0)
+ if (insn.reloc_arg[i] >= 0)
{
fixS *fixP;
bfd_reloc_code_real_type reloc = insn.reloc[i];
saw_prefix = 1;
param++;
}
-
+
if (arg == A_H) /* Channel */
{
if ((param[0] == 'c' || param[0] == 'C')
i.e. for code loaded at address 0 $toc will be 0. */
param += 4;
}
-
+
if (*param == '$')
{
/* Symbols can start with $, but if this symbol matches a register
if (np)
syntax_error_param = np;
}
-
+
save_ptr = input_line_pointer;
input_line_pointer = (char *) param;
expression (&insn->exp[reloc_i]);
if (emulate_apuasm)
{
- /* Convert the value to a format we expect. */
+ /* Convert the value to a format we expect. */
val <<= arg_encode[arg].rshift;
if (arg == A_U7A)
val = 173 - val;
else if (arg == A_U7B)
- val = 155 - val;
+ val = 155 - val;
}
if (high)
if (arg == A_U7A)
val = 173 - val;
else if (arg == A_U7B)
- val = 155 - val;
+ val = 155 - val;
/* Branch hints have a split encoding. Do the bottom part. */
if (arg == A_S11 || arg == A_S11I)
snprintf (output_invalid_buf, sizeof (output_invalid_buf),
"'%c'", c);
else
- snprintf (output_invalid_buf, sizeof (output_invalid_buf),
+ snprintf (output_invalid_buf, sizeof (output_invalid_buf),
"(0x%x)", (unsigned char) c);
return output_invalid_buf;
}
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to
- the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+ the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
/*
TODOs:
------
-
+
o .align cannot handle fill-data-width larger than 0xFF/8-bits. It
should be possible to define a 32-bits pattern.
/* This array holds the chars that only start a comment at the beginning of
a line. If the line seems to have the form '# 123 filename'
- .line and .file directives will appear in the pre-processed output.
+ .line and .file directives will appear in the pre-processed output.
Note that input_file.c hand checks for '#' at the beginning of the
first line of the input file. This is because the compiler outputs
- #NO_APP at the beginning of its output.
+ #NO_APP at the beginning of its output.
Also note that comments like this one will always work. */
const char line_comment_chars[] = "#*";
The code in this function is altered slightly to support floats
with 31-bits mantissas, thus the documentation below may be a
little bit inaccurate.
-
+
By Michael P. Hayes <m.hayes@elec.canterbury.ac.nz>
Here is how a generic floating point number is stored using
flonums (an extension of bignums) where p is a pointer to an
/* +INF: Replace with maximum float. */
if (precision == S_PRECISION)
words[0] = 0x77ff;
- else
+ else
{
words[0] = 0x7f7f;
words[1] = 0xffff;
/* -INF: Replace with maximum float. */
if (precision == S_PRECISION)
words[0] = 0x7800;
- else
+ else
words[0] = 0x7f80;
if (precision == E_PRECISION)
words[2] = 0x8000;
return return_value;
}
-static void
+static void
tic4x_insert_reg (char *regname, int regnum)
{
char buf[32];
&zero_address_frag));
}
-static void
+static void
tic4x_insert_sym (char *symname, int value)
{
symbolS *symbolP;
return s;
}
-static void
+static void
tic4x_emit_char (char c, int b)
{
expressionS exp;
emit_expr (&exp, b);
}
-static void
+static void
tic4x_seg_alloc (char *name ATTRIBUTE_UNUSED,
segT seg ATTRIBUTE_UNUSED,
int size,
}
/* .asg ["]character-string["], symbol */
-static void
+static void
tic4x_asg (int x ATTRIBUTE_UNUSED)
{
char c;
}
/* .bss symbol, size */
-static void
+static void
tic4x_bss (int x ATTRIBUTE_UNUSED)
{
char c;
}
/* Handle .byte, .word. .int, .long */
-static void
+static void
tic4x_cons (int bytes)
{
unsigned int c;
}
/* Handle .ascii, .asciz, .string */
-static void
+static void
tic4x_stringer (int append_zero)
{
int bytes;
}
/* .eval expression, symbol */
-static void
+static void
tic4x_eval (int x ATTRIBUTE_UNUSED)
{
char c;
}
/* Reset local labels. */
-static void
+static void
tic4x_newblock (int x ATTRIBUTE_UNUSED)
{
dollar_label_clear ();
/* .sect "section-name" [, value] */
/* .sect ["]section-name[:subsection-name]["] [, value] */
-static void
+static void
tic4x_sect (int x ATTRIBUTE_UNUSED)
{
char c;
}
/* symbol[:] .set value or .set symbol, value */
-static void
+static void
tic4x_set (int x ATTRIBUTE_UNUSED)
{
symbolS *symbolP;
}
/* [symbol] .usect ["]section-name["], size-in-words [, alignment-flag] */
-static void
+static void
tic4x_usect (int x ATTRIBUTE_UNUSED)
{
char c;
}
/* .version cpu-version. */
-static void
+static void
tic4x_version (int x ATTRIBUTE_UNUSED)
{
offsetT temp;
demand_empty_rest_of_line ();
}
-static void
+static void
tic4x_init_regtable (void)
{
unsigned int i;
}
}
-static void
+static void
tic4x_init_symbols (void)
{
/* The TI tools accept case insensitive versions of these symbols,
Source: TI: TMS320C3x/C4x Assembly Language Tools User's Guide,
1997, SPRU035C, p. 3-17/3-18. */
tic4x_insert_sym (".REGPARM", tic4x_reg_args);
- tic4x_insert_sym (".MEMPARM", !tic4x_reg_args);
+ tic4x_insert_sym (".MEMPARM", !tic4x_reg_args);
tic4x_insert_sym (".BIGMODEL", tic4x_big_model);
tic4x_insert_sym (".C30INTERRUPT", 0);
tic4x_insert_sym (".TMS320xx", tic4x_cpu == 0 ? 40 : tic4x_cpu);
}
/* Insert a new instruction template into hash table. */
-static int
+static int
tic4x_inst_insert (const tic4x_inst_t *inst)
{
static char prev_name[16];
}
/* Add instruction template, creating dynamic templates as required. */
-static int
+static int
tic4x_inst_add (const tic4x_inst_t *insts)
{
char *s = insts->name;
/* This function is called once, at assembler startup time. It should
set up all the tables, etc., that the MD part of the assembler will
need. */
-void
+void
md_begin (void)
{
int ok = 1;
tic4x_init_symbols ();
}
-void
+void
tic4x_end (void)
{
- bfd_set_arch_mach (stdoutput, bfd_arch_tic4x,
+ bfd_set_arch_mach (stdoutput, bfd_arch_tic4x,
IS_CPU_TIC4X (tic4x_cpu) ? bfd_mach_tic4x : bfd_mach_tic3x);
}
-static int
+static int
tic4x_indirect_parse (tic4x_operand_t *operand,
const tic4x_indirect_t *indirect)
{
return new_pointer;
}
-static int
+static int
tic4x_operands_match (tic4x_inst_t *inst, tic4x_insn_t *tinsn, int check)
{
const char *args = inst->args;
if (!(operand->mode == M_REGISTER))
break;
reg = exp->X_add_number;
- if ( (reg >= REG_R0 && reg <= REG_R7)
+ if ( (reg >= REG_R0 && reg <= REG_R7)
|| (IS_CPU_TIC4X (tic4x_cpu) && reg >= REG_R8 && reg <= REG_R11) )
INSERTU (opcode, reg, 7, 0);
else
if (operand->mode != M_REGISTER)
break;
reg = exp->X_add_number;
- if ( (reg >= REG_R0 && reg <= REG_R7)
+ if ( (reg >= REG_R0 && reg <= REG_R7)
|| (IS_CPU_TIC4X (tic4x_cpu) && reg >= REG_R8 && reg <= REG_R11) )
INSERTU (opcode, reg, 15, 8);
else
if (operand->mode != M_REGISTER)
break;
reg = exp->X_add_number;
- if ( (reg >= REG_R0 && reg <= REG_R7)
+ if ( (reg >= REG_R0 && reg <= REG_R7)
|| (IS_CPU_TIC4X (tic4x_cpu) && reg >= REG_R8 && reg <= REG_R11) )
INSERTU (opcode, reg, 15, 0);
else
if (operand->mode != M_REGISTER)
break;
reg = exp->X_add_number;
- if ( (reg >= REG_R0 && reg <= REG_R7)
+ if ( (reg >= REG_R0 && reg <= REG_R7)
|| (IS_CPU_TIC4X (tic4x_cpu) && reg >= REG_R8 && reg <= REG_R11) )
INSERTU (opcode, reg, 20, 16);
else
static void
tic4x_insn_check (tic4x_insn_t *tinsn)
{
-
+
if (!strcmp (tinsn->name, "lda"))
{
if (tinsn->num_operands < 2 || tinsn->num_operands > 2)
{
if (tinsn->num_operands < 4 || tinsn->num_operands > 5)
as_fatal ("Illegal internal %s insn definition", tinsn->name);
-
+
if (tinsn->operands[1].mode == M_REGISTER
&& tinsn->operands[tinsn->num_operands-1].mode == M_REGISTER
&& tinsn->operands[1].expr.X_add_number == tinsn->operands[tinsn->num_operands-1].expr.X_add_number )
}
}
-static void
+static void
tic4x_insn_output (tic4x_insn_t *tinsn)
{
char *dst;
}
/* Parse the operands. */
-static int
+static int
tic4x_operands_parse (char *s, tic4x_operand_t *operands, int num_operands)
{
if (!*s)
/* Assemble a single instruction. Its label has already been handled
by the generic front end. We just parse mnemonic and operands, and
produce the bytes of data and relocation. */
-void
+void
md_assemble (char *str)
{
int ok = 0;
s = str;
while (*s && *s != '|')
s++;
-
+
if (*s && s[1]=='|')
{
if(insn->parallel)
insn->in_use = 0;
return;
}
-
+
/* Lets take care of the first part of the parallel insn */
*s++ = 0;
md_assemble(str);
/* .. and let the second run though here */
}
}
-
+
if (str && insn->parallel)
{
/* Find mnemonic (second part of parallel instruction). */
return NULL;
}
-void
+void
md_apply_fix (fixS *fixP, valueT *value, segT seg ATTRIBUTE_UNUSED)
{
char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
}
/* Should never be called for tic4x. */
-void
+void
md_convert_frag (bfd *headers ATTRIBUTE_UNUSED,
segT sec ATTRIBUTE_UNUSED,
fragS *fragP ATTRIBUTE_UNUSED)
tic4x_reg_args = 0;
break;
- case 'r':
+ case 'r':
as_warn (_("Option -r is depreciated, please use -mregparm"));
case OPTION_REGPARM: /* register args */
tic4x_reg_args = 1;
/* This is called when a line is unrecognized. This is used to handle
definitions of TI C3x tools style local labels $n where n is a single
decimal digit. */
-int
+int
tic4x_unrecognized_line (int c)
{
int lab;
return size; /* Byte (i.e., 32-bit) alignment is fine? */
}
-static int
+static int
tic4x_pc_offset (unsigned int op)
{
/* Determine the PC offset for a C[34]x instruction.
/* Fill the alignment area with NOP's on .text, unless fill-data
was specified. */
-int
+int
tic4x_do_align (int alignment,
const char *fill,
int len,
{
/* Because we are talking lwords, not bytes, adjust alignment to do words */
alignment += 2;
-
+
if (alignment != 0 && !need_pass_2)
{
if (fill == NULL)
else
frag_align_pattern (alignment, fill, len, max);
}
-
+
/* Return 1 to skip the default alignment function */
return 1;
}
/* Look for and remove parallel instruction operator ||. */
-void
+void
tic4x_start_line (void)
{
char *s = input_line_pointer;
/* tc-tic4x.h -- Assemble for the Texas TMS320C[34]X.
Copyright (C) 1997-2015 Free Software Foundation, Inc.
-
+
Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
This file is part of GAS, the GNU Assembler.
case BFD_RELOC_C6000_PCR_H16:
case BFD_RELOC_C6000_PCR_L16:
return 0;
-
+
default:
return 1;
}
static const int
-tic6x_unwind_frame_regs[TIC6X_NUM_UNWIND_REGS] =
+tic6x_unwind_frame_regs[TIC6X_NUM_UNWIND_REGS] =
/* A15 B15 B14 B13 B12 B11 B10 B3 A14 A13 A12 A11 A10. */
{ 15, 31, 30, 29, 28, 27, 26, 19, 14, 13, 12, 11, 10 };
/* Register save offsets for __c6xabi_push_rts. */
static const int
-tic6x_pop_rts_offset_little[TIC6X_NUM_UNWIND_REGS] =
+tic6x_pop_rts_offset_little[TIC6X_NUM_UNWIND_REGS] =
/* A15 B15 B14 B13 B12 B11 B10 B3 A14 A13 A12 A11 A10. */
{ -1, 1, 0, -3, -4, -7, -8,-11, -2, -5, -6, -9,-10};
static const int
-tic6x_pop_rts_offset_big[TIC6X_NUM_UNWIND_REGS] =
+tic6x_pop_rts_offset_big[TIC6X_NUM_UNWIND_REGS] =
/* A15 B15 B14 B13 B12 B11 B10 B3 A14 A13 A12 A11 A10. */
{ -2, 1, 0, -4, -3, -8, -7,-12, -1, -6, -5,-10, -9};
continue;
unwind->saved_reg_count++;
- /* Encoding uses 4 bits per word, so size of unwinding opcode data
+ /* Encoding uses 4 bits per word, so size of unwinding opcode data
limits the save area size. The exact cap will be figured out
later due to overflow, the 0x800 here is just a quick sanity
check to weed out obviously excessive offsets. */
/* Out of range conditional branch. Emit a branch around a 22bit jump. */
else if (fragP->fr_subtype == SUBYPTE_COND_9_22 + 1
|| fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 1
- || fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 2
+ || fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 2
|| fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 2)
{
unsigned char *buffer =
ban these opcodes. They are mnemonics for "elastic" instructions
that are supposed to assemble into the fewest bytes needed to do a
branch, or to do a conditional branch, or whatever.
-
+
The opcode is in the usual place [low-order n*8 bits]. This means
that if you mask off the bucky bits, the usual rules apply about
how long the opcode is.
-
+
All VAX branch displacements come at the end of the instruction.
For simple branches (1-byte opcode + 1-byte displacement) the last
operand is coded 'b?' where the "data type" '?' is a clue that we
and branch around a jump. This is by far the most common case.
That is why the VIT_OPCODE_SYNTHETIC bit is set: it says this is
a 0-byte op-code followed by 2 or more bytes of operand address.
-
+
If the op-code has VIT_OPCODE_SPECIAL set, then we have a more unusual
case.
-
+
For JBSB & JBR the treatment is the similar, except (1) we have a 'bw'
option before (2) we can directly JSB/JMP because there is no condition.
These operands have 'b-' as their access/data type.
-
+
That leaves a bunch of random opcodes: JACBx, JxOBxxx. In these
cases, we do the same idea. JACBxxx are all marked with a 'b!'
JAOBxxx & JSOBxxx are marked with a 'b:'. */
/* Take 3 char.s, the last of which may be `\0` (non-existent)
and return the VAX register number that they represent.
-
+
Return -1 if they don't form a register name. Good names return
a number from 0:15 inclusive.
-
+
Case is not important in a name.
-
+
Register names understood are:
-
+
R0
R1
R2
For speed, expect a string of whitespace to be reduced to a single ' '.
This is the case for GNU AS, and is easy for other DEC-compatible
assemblers.
-
+
Knowledge about DEC VAX assembler operand notation lives here.
This doesn't even know what a register name is, except it believes
all register names are 2 or 3 characters, and lets vax_reg_parse() say
what number each name represents.
It does, however, know that PC, SP etc are special registers so it can
detect addressing modes that are silly for those registers.
-
+
Where possible, it delivers 1 fatal or 1 warning message if the operand
is suspect. Exactly what we test for is still evolving.
---
Arg block.
-
+
There were a number of 'mismatched argument type' bugs to vip_op.
The most general solution is to typedef each (of many) arguments.
We used instead a typedef'd argument block. This is less modular
on most engines, and seems to keep programmers happy. It will have
to be done properly if we ever want to use vip_op as a general-purpose
module (it was designed to be).
-
+
G^
Doesn't support DEC "G^" format operands. These always take 5 bytes
If there is some other use for "G^", feel free to code it in!
speed
-
+
If I nested if()s more, I could avoid testing (*err) which would save
time, space and page faults. I didn't nest all those if()s for clarity
and because I think the mode testing can be re-arranged 1st to test the
- commoner constructs 1st. Does anybody have statistics on this?
-
+ commoner constructs 1st. Does anybody have statistics on this?
+
error messages
-
+
In future, we should be able to 'compose' error messages in a scratch area
and give the user MUCH more informative error messages. Although this takes
a little more code at run-time, it will make this module much more self-
the Un*x characters "$`*", that most users will expect from this AS.
----
-
+
The input is a string, ending with '\0'.
-
+
We also require a 'hint' of what kind of operand is expected: so
we can remind caller not to write into literals for instance.
-
+
The output is a skeletal instruction.
-
+
The algorithm has two parts.
1. extract the syntactic features (parse off all the @^#-()+[] mode crud);
2. express the @^#-()+[] as some parameters suited to further analysis.
-
+
2nd step is where we detect the googles of possible invalid combinations
a human (or compiler) might write. Note that if we do a half-way
decent assembler, we don't know how long to make (eg) displacement
- error text(s) why we couldn't understand the operand
----
-
+
To decode output of this, test errtxt. If errtxt[0] == '\0', then
we had no errors that prevented parsing. Also, if we ever report
an internal bug, errtxt[0] is set non-zero. So one test tells you
if the other outputs are to be taken seriously.
----
-
+
Dec defines the semantics of address modes (and values)
by a two-letter code, explained here.
-
+
letter 1: access type
-
+
a address calculation - no data access, registers forbidden
b branch displacement
m read - let go of bus - write back "modify"
v bit field address: like 'a' but registers are OK
w write
space no operator (eg ".long foo") [our convention]
-
+
letter 2: data type (i.e. width, alignment)
-
+
b byte
d double precision floating point (D format)
f single precision floating point (F format)
? simple synthetic branch operand
- unconditional synthetic JSB/JSR operand
! complex synthetic branch operand
-
+
The '-?!' letter 2's are not for external consumption. They are used
for various assemblers. Generally, all unknown widths are assumed 0.
We don't limit your choice of width character.
-
+
DEC operands are hard work to parse. For example, '@' as the first
character means indirect (deferred) mode but elsewhere it is a shift
operator.
We try hard not to parse anything that MIGHT be part of the expression
buried in that syntax. For example if we see @...(Rn) we don't check
for '-' before the '(' because mode @-(Rn) does not exist.
-
+
After parsing we have:
-
+
at 1 if leading '@' (or Un*x '*')
len takes one value from " bilsw". eg B^ -> 'b'.
hash 1 if leading '#' (or Un*x '$')
paren 1 if () are around register
reg major register number 0:15 -1 means absent
ndx index register number 0:15 -1 means absent
-
+
Again, I dare not explain it: just trace ALL the code!
Summary of vip_op outputs.
/* p points to what may be the beginning of an expression.
We have peeled off the front all that is peelable.
We know at, len, hash.
-
+
Lets point q at the end of the text and parse that (backwards). */
for (q = p; *q; q++)
We will deliver a 4-bit reg, and a 4-bit mode. */
/* Case of branch operand. Different. No L^B^W^I^S^ allowed for instance.
-
+
in: at ?
len ?
hash ?
paren ?
reg ?
ndx ?
-
+
out: mode 0
reg -1
len ' '
/* Since nobody seems to use it: comment this 'feature'(?) out for now. */
#ifdef NEVER
/* Case of stand-alone operand. e.g. ".long foo"
-
+
in: at ?
len ?
hash ?
paren ?
reg ?
ndx ?
-
+
out: mode 0
reg -1
len ' '
#endif
/* Case of S^#.
-
+
in: at 0
len 's' definition
hash 1 demand
paren 0 by "()" scan logic because "S^" seen
reg -1 or nn by mistake
ndx -1
-
+
out: mode 0
reg -1
len 's'
err = _("S^# may only read-access");
}
}
-
+
/* Case of -(Rn), which is weird case.
-
+
in: at 0
len '
hash 0
paren 1 by definition
reg present by definition
ndx optional
-
+
out: mode 7
reg present
len ' '
}
/* Case of (Rn)+, which is slightly different.
-
+
in: at
len ' '
hash 0
paren 1 by definition
reg present by definition
ndx optional
-
+
out: mode 8+@
reg present
len ' '
}
/* Case of #, without S^.
-
+
in: at
len ' ' or 'i'
hash 1 by definition
paren 0
reg absent
ndx optional
-
+
out: mode 8+@
reg PC
len ' ' or 'i'
/* Case of Rn. We separate this one because it has a few special
errors the remaining modes lack.
-
+
in: at optional
len ' '
hash 0 by program logic
paren 0 by definition
reg present by definition
ndx optional
-
+
out: mode 5+@
reg present
len ' ' enforce no length
paren == 1 OR reg==-1 */
/* Rest of cases fit into one bunch.
-
+
in: at optional
len ' ' or 'b' or 'w' or 'l'
hash 0 by program logic
paren optional
reg optional
ndx optional
-
+
out: mode 10 + @ + len
reg optional
len ' ' or 'b' or 'w' or 'l'
knowledge of how you parse (or evaluate) your expressions.
We do however strip off and decode addressing modes and operation
mnemonic.
-
+
The exploded instruction is returned to a struct vit of your choice.
#include "vax-inst.h" to know what a struct vit is.
-
+
This function's value is a string. If it is not "" then an internal
logic error was found: read this code to assign meaning to the string.
No argument string should generate such an error string:
it means a bug in our code, not in the user's text.
-
+
You MUST have called vip_begin() once before using this function. */
static void
if (*instring == ' ')
++instring;
-
+
/* MUST end in end-of-string or exactly 1 space. */
for (p = instring; *p && *p != ' '; p++)
;
/* tc-xc16x.c -- Assembler for the Infineon XC16X.
Copyright (C) 2006-2015 Free Software Foundation, Inc.
- Contributed by KPIT Cummins Infosystems
+ Contributed by KPIT Cummins Infosystems
This file is part of GAS, the GNU Assembler.
*valP = 256 - (*valP);
}
}
-
+
gas_cgen_md_apply_fix (fixP, valP, seg);
return;
}
/* This file is tc-xc16x.h
Copyright (C) 2006-2015 Free Software Foundation, Inc.
- Contributed by KPIT Cummins Infosystems
+ Contributed by KPIT Cummins Infosystems
This file is part of GAS, the GNU Assembler.
/* This can happen when gcc is generating debug output.
For example it can create a stab with the address of
a function:
-
+
.stabs "foo:F(0,21)",36,0,0,@fptr(foo)
-
+
Since this does not involve switching code pages, we
just allow the reloc to be generated without any
@fptr behaviour. */
|| xstormy16_force_relocation (fixP))
/* The symbol is undefined,
or it is defined but not in this section,
- or the relocation will be relative to this symbol not the section symbol.
+ or the relocation will be relative to this symbol not the section symbol.
Let the linker figure it out. */
return 0;
{
struct suffix_reloc_map *sfx;
unsigned char operator = (unsigned char) -1;
-
+
for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++)
{
if (sfx->reloc == reloc)
}
/* Don't do anything special with NOPs inside FLIX instructions. They
- are handled elsewhere. Real NOP instructions are always available
+ are handled elsewhere. Real NOP instructions are always available
in configurations with FLIX, so this should never be an issue but
check for it anyway. */
if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED
if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand)
== 1)
as_bad_where ((char *) file, line,
- _("operand %d of '%s' has out of range value '%u'"),
+ _("operand %d of '%s' has out of range value '%u'"),
operand + 1,
xtensa_opcode_name (xtensa_default_isa, opcode),
value);
if (frag->fr_fix == 0)
frag = next_non_empty_frag (frag);
-
+
if (frag)
{
xtensa_insnbuf_from_chars
fmt = xtensa_format_decode (isa, insnbuf);
op_size = xtensa_format_length (isa, fmt);
frag_addr = frag->fr_address % xtensa_fetch_width;
-
+
if (frag_addr + op_size > xtensa_fetch_width)
as_warn_where (frag->fr_file, frag->fr_line,
_("unaligned loop: %d bytes at 0x%lx"),
xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount");
xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti");
- for (i = 0; i < xtensa_isa_num_formats (isa); i++)
+ for (i = 0; i < xtensa_isa_num_formats (isa); i++)
{
int format_slots = xtensa_format_num_slots (isa, i);
if (format_slots > config_max_slots)
symbolS *expr_symbols = NULL;
-void
+void
xtensa_symbol_new_hook (symbolS *sym)
{
if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section)
/* Handle a corner case that comes up in hardware
diagnostics. The original assembly looks like this:
-
+
loop aX, LabelA
<empty_frag>--not found by next_non_empty_frag
loop aY, LabelB
{
if (loop_frag->fr_type == rs_machine_dependent
&& (loop_frag->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
- || loop_frag->fr_subtype
+ || loop_frag->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE))
targ_frag = loop_frag;
else
sleb128 value, the linker is unable to adjust that value to account for
link-time relaxation. Mark all the code between such symbols so that
its size cannot be changed by linker relaxation. */
-
+
static void
xtensa_mark_difference_of_two_symbols (void)
{
symbolS *expr_sym;
- for (expr_sym = expr_symbols; expr_sym;
+ for (expr_sym = expr_symbols; expr_sym;
expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol)
{
expressionS *exp = symbol_get_value_expression (expr_sym);
{
symbolS *left = exp->X_add_symbol;
symbolS *right = exp->X_op_symbol;
-
+
/* Difference of two symbols not in the same section
are handled with relocations in the linker. */
if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right))
fragS *end;
fragS *walk;
- if (symbol_get_frag (left)->fr_address
+ if (symbol_get_frag (left)->fr_address
<= symbol_get_frag (right)->fr_address)
{
start = symbol_get_frag (left);
walk = start->tc_frag_data.no_transform_end;
else
walk = start;
- do
+ do
{
walk->tc_frag_data.is_no_transform = 1;
walk = walk->fr_next;
for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
{
if (fragP->fr_type == rs_machine_dependent
- && fragP->fr_subtype == RELAX_SLOTS
+ && fragP->fr_subtype == RELAX_SLOTS
&& fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
{
static xtensa_insnbuf insnbuf = NULL;
int extra_bytes;
int bytes_short = desired_diff - num_widens;
- gas_assert (desired_diff >= 0
+ gas_assert (desired_diff >= 0
&& desired_diff < (signed) xtensa_fetch_width);
if (desired_diff == 0)
return 0;
/* The first instruction in the relaxed sequence will go after
the current wide instruction, and thus its symbolic immediates
might not fit. */
-
+
istack_init (&istack);
- num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP,
+ num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP,
frag_offset + old_size,
min_steps, stretch + old_size);
gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS);
- fragP->tc_frag_data.slot_subtypes[slot]
+ fragP->tc_frag_data.slot_subtypes[slot]
= (int) RELAX_IMMED + num_steps;
num_literal_bytes = get_num_stack_literal_bytes (&istack);
- literal_diff
+ literal_diff
= num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
-
+
num_text_bytes = get_num_stack_text_bytes (&istack) + old_size;
}
}
{
const char *gname = inf;
const char *group_name = elf_group_name (sec);
-
+
return (group_name == gname
|| (group_name != NULL
&& gname != NULL
if (*pcached)
return *pcached;
-
+
text_name = default_lit_sections.lit_prefix;
if (! text_name || ! *text_name)
{
{
int i;
- memset (v, 0, offsetof (vliw_insn, slots)
+ memset (v, 0, offsetof (vliw_insn, slots)
+ sizeof(TInsn) * config_max_slots);
v->format = XTENSA_UNDEFINED;
static void
xg_copy_vinsn (vliw_insn *dst, vliw_insn *src)
{
- memcpy (dst, src,
+ memcpy (dst, src,
offsetof(vliw_insn, slots) + src->num_slots * sizeof(TInsn));
dst->insnbuf = src->insnbuf;
memcpy (dst->slotbuf, src->slotbuf, src->num_slots * sizeof(xtensa_insnbuf));
/* When the code density option is available, this will generate a
NOP.N marked RELAX_NARROW. Otherwise, it will create an rs_fill
fragment with a NOP in it. Once a frag has been converted to
- RELAX_LOOP_END_ADD_NOP, it should never be changed back to
+ RELAX_LOOP_END_ADD_NOP, it should never be changed back to
RELAX_LOOP_END. */
RELAX_LITERAL,
RELAX_UNREACHABLE frag. */
RELAX_ORG,
- /* This marks the location as having previously been an rs_org frag.
+ /* This marks the location as having previously been an rs_org frag.
rs_org frags are converted to fill-zero frags immediately after
relaxation. However, we need to remember where they were so we can
prevent the linker from changing the size of any frag between the
}
/* Check whether a symbol involves a register. */
-static int
+static int
contains_register(symbolS *sym)
{
if (sym)
{
expressionS * ex = symbol_get_value_expression(sym);
- return (O_register == ex->X_op)
- || (ex->X_add_symbol && contains_register(ex->X_add_symbol))
+ return (O_register == ex->X_op)
+ || (ex->X_add_symbol && contains_register(ex->X_add_symbol))
|| (ex->X_op_symbol && contains_register(ex->X_op_symbol));
}
else
BFD_RELOC_32
};
- if (nbytes < 1 || nbytes > 4)
+ if (nbytes < 1 || nbytes > 4)
{
as_bad (_("unsupported BFD relocation size %u"), nbytes);
}
{ "d32", cons, 4},
{ "def24", cons, 3},
{ "def32", cons, 4},
- { "defb", emit_data, 1},
+ { "defb", emit_data, 1},
{ "defs", s_space, 1}, /* Synonym for ds on some assemblers. */
{ "defw", cons, 2},
{ "ds", s_space, 1}, /* Fill with bytes rather than words. */
}
else if ((*p) && (!ISSPACE (*p)))
as_bad (_("syntax error"));
- else
+ else
{
buf[i] = 0;
p = skip_space (p);
key = buf;
-
+
insp = bsearch (&key, instab, ARRAY_SIZE (instab),
sizeof (instab[0]), key_cmp);
if (!insp)
if (val > 255 || val < -128)
as_warn_where (fixP->fx_file, fixP->fx_line, _("overflow"));
*p_lit++ = val;
- fixP->fx_no_overflow = 1;
+ fixP->fx_no_overflow = 1;
if (fixP->fx_addsy == NULL)
fixP->fx_done = 1;
break;
case BFD_RELOC_16:
*p_lit++ = val;
*p_lit++ = (val >> 8);
- fixP->fx_no_overflow = 1;
+ fixP->fx_no_overflow = 1;
if (fixP->fx_addsy == NULL)
fixP->fx_done = 1;
break;
*p_lit++ = val;
*p_lit++ = (val >> 8);
*p_lit++ = (val >> 16);
- fixP->fx_no_overflow = 1;
+ fixP->fx_no_overflow = 1;
if (fixP->fx_addsy == NULL)
fixP->fx_done = 1;
break;
P2VAR to the truncated power of two of sizes up to eight bytes. */
#define TC_IMPLICIT_LCOMM_ALIGNMENT(SIZE, P2VAR) (P2VAR) = 0
-/* It does not make any sense to perform arithmetic on the numbers
+/* It does not make any sense to perform arithmetic on the numbers
we use to identify registers. */
#define md_register_arithmetic 0
/* This file is te-generic.h and is intended to be a template for
target environment specific header files.
-
+
It is my intent that this file will evolve into a file suitable for config,
compile, and copying as an aid for testing and porting. xoxorich. */
static char buff [255 + 7];
vms_file_stats_name (dirname, filename, 0, 0, 0, &ver);
- snprintf (buff, 255 + 7, "%s;%d", filename, ver);
+ snprintf (buff, 255 + 7, "%s;%d", filename, ver);
return buff;
}
addi.n a4, 0x1010
=> addi a4, 0x1010
=> addmi a4, 0x1010
- => addmi a4, 0x1000, addi a4, 0x10.
+ => addmi a4, 0x1000, addi a4, 0x10.
See the comments in xg_assembly_relax for some important details
regarding how these chains must be built. */
out-of-range branch. Put the wide branch relaxations first in the
table since they are more efficient than the branch-around
relaxations. */
-
+
{"beqz %as,%label ? IsaUseWideBranches", "WIDE.beqz %as,%label"},
{"bnez %as,%label ? IsaUseWideBranches", "WIDE.bnez %as,%label"},
{"bgez %as,%label ? IsaUseWideBranches", "WIDE.bgez %as,%label"},
{"bnall %as,%at,%label ? IsaUseWideBranches", "WIDE.bnall %as,%at,%label"},
{"bbc %as,%at,%label ? IsaUseWideBranches", "WIDE.bbc %as,%at,%label"},
{"bbs %as,%at,%label ? IsaUseWideBranches", "WIDE.bbs %as,%at,%label"},
-
+
/* Widening branch comparisons eq/ne to zero. Prefer relaxing to narrow
branches if the density option is available. */
{"beqz %as,%label ? IsaUseDensityInstruction", "bnez.n %as,%LABEL;j %label;LABEL"},
else if (!strcmp (option_name, "Loops"))
option_available = (XCHAL_HAVE_LOOPS == 1);
else if (!strcmp (option_name, "WideBranches"))
- option_available
+ option_available
= (XCHAL_HAVE_WIDE_BRANCHES == 1 && produce_flix == FLIX_ALL);
else if (!strcmp (option_name, "PredictedBranches"))
option_available
precond_e *precond;
insn_repl_e *r;
- if (!wide_branch_opcode (initial_insn->t.opcode_name, ".w18", &opcode)
+ if (!wide_branch_opcode (initial_insn->t.opcode_name, ".w18", &opcode)
&& !wide_branch_opcode (initial_insn->t.opcode_name, ".w15", &opcode))
opcode = xtensa_opcode_lookup (isa, initial_insn->t.opcode_name);
dnl it under the terms of the GNU General Public License as published by
dnl the Free Software Foundation; either version 3 of the License, or
dnl (at your option) any later version.
-dnl
+dnl
dnl This program is distributed in the hope that it will be useful,
dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
dnl GNU General Public License for more details.
-dnl
+dnl
dnl You should have received a copy of the GNU General Public License
dnl along with this program; see the file COPYING3. If not see
dnl <http://www.gnu.org/licenses/>.
$! This file sets things up to build gas on a VMS system to generate object
$! files for a VMS system. We do not use the configure script, since we
$! do not have /bin/sh to execute it.
-$!
+$!
$! Copyright (C) 2012-2015 Free Software Foundation, Inc.
$!
$! This file is free software; you can redistribute it and/or modify
$! it under the terms of the GNU General Public License as published by
$! the Free Software Foundation; either version 3 of the License, or
$! (at your option) any later version.
-$!
+$!
$! This program is distributed in the hope that it will be useful,
$! but WITHOUT ANY WARRANTY; without even the implied warranty of
$! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
$! GNU General Public License for more details.
-$!
+$!
$! You should have received a copy of the GNU General Public License
$! along with this program; see the file COPYING3. If not see
$! <http://www.gnu.org/licenses/>.
$ LIBIBERTY = ",[-.libiberty]libiberty.olb/lib"
$ LIBOPCODES = ",[-.opcodes]libopcodes.olb/lib"
$!
-$ AS_OBJS="targ-cpu," + FILES
+$ AS_OBJS="targ-cpu," + FILES
$!
$ write sys$output "CFLAGS=",CFLAGS
$!
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
-#
+#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
moxie-*-uclinux) fmt=elf em=linux ;;
moxie-*-moxiebox*) fmt=elf endian=little ;;
moxie-*-*) fmt=elf ;;
-
+
mt-*-elf) fmt=elf bfd_gas=yes ;;
msp430-*-*) fmt=elf ;;
visium-*-elf) fmt=elf ;;
xstormy16-*-*) fmt=elf ;;
-
+
xgate-*-*) fmt=elf ;;
xtensa*-*-*) fmt=elf ;;
section, as well as our sub-sections, and we have to ensure
that all of the sub-sections are merged into a proper
.debug_line section before a debugger sees them. */
-
+
sec_name = bfd_get_section_name (stdoutput, seg);
if (strcmp (sec_name, ".text") != 0)
{
the Free Software Foundation; either version 3, or (at your option)
any later version.
- GAS is distributed in the hope that it will be useful,
+ GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
}
";"|"#" {
int c;
- while ((c = input ()) != EOF)
+ while ((c = input ()) != EOF)
{
- if (c == '\n')
+ if (c == '\n')
{
unput (c);
break;
}
}
}
-"\n" {
- insntbl_line++;
+"\n" {
+ insntbl_line++;
MDBG (("in lex, NL = %d (x%x)\n", NL, NL));
- return NL;
+ return NL;
}
-" "|"\t" {
+" "|"\t" {
}
. {
MDBG (("char = %x, %d\n", yytext[0], yytext[0]));
%%
#ifndef yywrap
-int
-yywrap ()
- {
- return 1;
+int
+yywrap ()
+ {
+ return 1;
}
#endif
%{
-/*
+/*
Yacc grammar for instruction table entries.
it starts. Using the information in the table, the assembler
generates an internal list of valid coprocessor registers and
functions. The assembler uses this internal list in addition to the
-standard MIPS registers and instructions which are built-in to the
+standard MIPS registers and instructions which are built-in to the
assembler during code generation.
To specify the coprocessor table when invoking the GNU assembler, use
entrydef -> type name val
entrydef -> 'insn' name val funcdef ; type of entry (instruction)
- z -> 'p'['0'..'3'] ; processor number
+ z -> 'p'['0'..'3'] ; processor number
type -> ['dreg' | 'creg' | 'greg' ] ; type of entry (register)
; 'dreg', 'creg' or 'greg' specifies a data, control, or general
; register mnemonic, respectively
field -> [','] ftype frange flags
flags -> ['*' flagexpr]
flagexpr -> '[' flagexpr ']'
- flagexpr -> val '|' flagexpr
+ flagexpr -> val '|' flagexpr
ftype -> [ type | 'immed' | 'addr' ]
; 'immed' specifies an immediate value; see grammar for "val" above
- ; 'addr' specifies a C identifier; name of symbol to be resolved at
+ ; 'addr' specifies a C identifier; name of symbol to be resolved at
; link time
frange -> ':' val '-' val ; starting to ending bit positions, where
; where 0 is least significant bit
comment -> [';'|'#'] [char]*
char -> any printable character
- ltr -> ['a'..'z'|'A'..'Z']
+ ltr -> ['a'..'z'|'A'..'Z']
dec -> ['0'..'9']* ; value in decimal
- hex -> '0x'['0'..'9' | 'a'..'f' | 'A'..'F']* ; value in hexadecimal
+ hex -> '0x'['0'..'9' | 'a'..'f' | 'A'..'F']* ; value in hexadecimal
Examples
p1 dreg d1 1 ; data register "d1" for COP1 has value 1
p1 creg c3 3 ; ctrl register "c3" for COP1 has value 3
- p3 func fill 0x1f:24-20 ; function "fill" for COP3 has value 31 and
+ p3 func fill 0x1f:24-20 ; function "fill" for COP3 has value 31 and
; no fields
will allow the assembler to accept the following coprocessor instructions:
LWC1 d1,0x100 ($2)
fill
-Here, the general purpose register "$2", and instruction "LWC1", are standard
-mnemonics built-in to the MIPS assembler.
+Here, the general purpose register "$2", and instruction "LWC1", are standard
+mnemonics built-in to the MIPS assembler.
Example 2:
p3 dreg d3 3 ; data register "d3" for COP3 has value 3
p3 creg c2 22 ; control register "c2" for COP3 has value 22
- p3 func fee 0x1f:24-20 dreg:17-13 creg:12-8 immed:7-0
- ; function "fee" for COP3 has value 31, and 3 fields
- ; consisting of a data register, a control register,
+ p3 func fee 0x1f:24-20 dreg:17-13 creg:12-8 immed:7-0
+ ; function "fee" for COP3 has value 31, and 3 fields
+ ; consisting of a data register, a control register,
; and an immediate value.
will allow the assembler to accept the following coprocessor instruction:
31-26 25 24-20 19-18 17-13 12-8 7-0
COPz CO fun dreg creg immed
- 010011 1 11111 00 00011 10110 00000001
+ 010011 1 11111 00 00011 10110 00000001
0x4ff07601
and will emit the object code:
31-26 25 24-20 19-18 17-13 12-8 7-0
- COPz CO fun dreg creg
- 010011 1 11111 00 00011 10110 00000001
+ COPz CO fun dreg creg
+ 010011 1 11111 00 00011 10110 00000001
0x4ff07601
Encoding of ranges:
To handle more than one bit position range within an instruction,
use 0s to mask out the ranges which don't apply.
-May decide to modify the syntax to allow commas separate multiple
+May decide to modify the syntax to allow commas separate multiple
ranges within an instruction (range','range).
Changes in grammar:
was deleted from the original format such that we now count the fields.
----
-FIXME! should really change lexical analyzer
+FIXME! should really change lexical analyzer
to recognize 'dreg' etc. in context sensitive way.
Currently function names or mnemonics may be incorrectly parsed as keywords
#if DBG_LVL >= 1
#define DBG(x) printf x
#else
-#define DBG(x)
+#define DBG(x)
#endif
#if DBG_LVL >= 2
#define DBGL2(x) printf x
#else
-#define DBGL2(x)
+#define DBGL2(x)
#endif
static int sbit, ebit;
%}
-%union
+%union
{
char *str;
int num;
entry:
pnum regtype name value NL
{
- DBG (("line %d: entry pnum=%d type=%d name=%s value=x%x\n",
+ DBG (("line %d: entry pnum=%d type=%d name=%s value=x%x\n",
insntbl_line, $1, $2, $3, $4));
itbl_add_reg ($1, $2, $3, $4);
}
;
ftype:
- regtype
+ regtype
{
DBGL2 (("ftype\n"));
$$ = $1;
}
- | ADDR
+ | ADDR
{
DBGL2 (("addr\n"));
$$ = ADDR;
fieldspec:
ftype range flags
{
- DBG (("line %d: field type=%d sbit=%d ebit=%d, flags=0x%x\n",
+ DBG (("line %d: field type=%d sbit=%d ebit=%d, flags=0x%x\n",
insntbl_line, $1, sbit, ebit, $3));
itbl_add_operand (insn, $1, sbit, ebit, $3);
}
DBGL2 (("flags=%d\n", $2));
$$ = $2;
}
- |
+ |
{
$$ = 0;
}
ebit = 0;
}
;
-
+
pnum:
PNUM
{
ID
{
DBGL2 (("name=%s\n",$1));
- $$ = $1;
+ $$ = $1;
}
;
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
-#
+#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
projects / binutils-gdb.git / commitdiff