add standards tags

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 7595ce738429f2139d2fc5e9711fea5535a2b9ed..f8c84cc36e422605a88f3b0c5b54d96e3b29b50c 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # Simple-V Vectorisation for the OpenPOWER ISA
 
 **SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER Foundation ISA WG for review.

diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn
index 6b428cf3118a6652500e8acae67455ef5c837883..2a302ea5d7d9929ad1e50f3cc37bf47622964086 100644 (file)
--- a/openpower/sv/16_bit_compressed.mdwn
+++ b/openpower/sv/16_bit_compressed.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # 16 bit Compressed
 
 Similar to VLE (but without immediate-prefixing) this encoding is designed

diff --git a/openpower/sv/av_opcodes.mdwn b/openpower/sv/av_opcodes.mdwn
index a5bfadde282a5d34025c74ad7ebd2e5978b11d49..e91ce6ede0da42a3483f9fdc7d4c6748efde43f4 100644 (file)
--- a/openpower/sv/av_opcodes.mdwn
+++ b/openpower/sv/av_opcodes.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # Scalar OpenPOWER Audio and Video Opcodes
 
 the fundamental principle of SV is a hardware for-loop. therefore the first (and in nearly 100% of cases only) place to put Vector operations is first and foremost in the *scalar* ISA.  However only by analysing those scalar opcodes *in* a SV Vectorisation context does it become clear why they are needed and how they may be designed.

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index 0d6331be37a3cc6a26a5cfd347fada305c1ca821..f80b17eda6a422b465e7c56fdf4f1dff18e4d4c8 100644 (file)
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # bit to byte permute
 
     do j = 0 to 7

diff --git a/openpower/sv/byteswap.mdwn b/openpower/sv/byteswap.mdwn
index b80de7ef3bf89f95f74133eb77412209c233c0a4..194e485026f638d40a717b25607bc18c4c34d420 100644 (file)
--- a/openpower/sv/byteswap.mdwn
+++ b/openpower/sv/byteswap.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # Byte-swapping
 
 ## Byte-swapping Mux

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index f8faa63880ab53a8a99df5cce2c46e710ddc010c..f6213096b64d3b23ddfd0c61583eb064daa27868 100644 (file)
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # New instructions for CR/INT predication
 
 See:

diff --git a/openpower/sv/fcvt.mdwn b/openpower/sv/fcvt.mdwn
index 332e10ea75c6907b1e18c23dc6a6993cd1656482..27de2900e082aa566225acbd7b7678366d0cd64b 100644 (file)
--- a/openpower/sv/fcvt.mdwn
+++ b/openpower/sv/fcvt.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # SV FP Conversion
 
 OpenPOWER Scalar ISA requires that FP32 numbers be distributed throughout the bits of the underlying FP64 register such that at any time an FP64 opcode nay be used, without performing any kind of conversion, directly on that FP32 value.  Likewise if precision is not important an FP32 opcode may be called on an FP64 value without conversion needed.

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 900e16f5abe333dffd45a3cadcbc41185952a411..ee4c11f6fa33f19f5601a17f2a4214fb7910df88 100644 (file)
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # SV Load and Store
 
 Links:

diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index 3a4f3c3e665fe6815dcb545942cb52bc2a989313..0566c6f2585ce32900eaf0666550110dad5fbd97 100644 (file)
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # mv.swizzle
 
 Links

diff --git a/openpower/sv/mv.vec.mdwn b/openpower/sv/mv.vec.mdwn
index ce7d1310bb2d4e49f1fd12438bec412eea6a9f0e..0210b7d620eac447ee2b67b4ab259862d8a5e3ba 100644 (file)
--- a/openpower/sv/mv.vec.mdwn
+++ b/openpower/sv/mv.vec.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # Vector mv operations
 
 In the SIMD VSX set, section 6.8.1 and 6.8.2 p254 of v3.0B has a series of pack and unpack operations. This page covers those and more.  [[svp64]] provides the Vector Context to also add saturation as well as predication.

diff --git a/openpower/sv/mv.x.mdwn b/openpower/sv/mv.x.mdwn
index 62249bb073b2a3f23776e94f30efd70a0d2d62ed..fcb7657f1ba38976b4697bb749e530f5e1793a35 100644 (file)
--- a/openpower/sv/mv.x.mdwn
+++ b/openpower/sv/mv.x.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # mv.x
 
 TODO

diff --git a/openpower/sv/propagation.mdwn b/openpower/sv/propagation.mdwn
index 9778d1b8908659cb161b579821f6e59283cb737e..85b59f8f56a24805d573314e0fb7c2adffcb17bf 100644 (file)
--- a/openpower/sv/propagation.mdwn
+++ b/openpower/sv/propagation.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # SV Context Propagation
 
 [[!toc]]

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index be24a160921a3062ab19d6d681f7edcd24e1c27c..efb05e898f7ced0f0db36c5618810475794e5648 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # OpenPOWER SV setvl/setvli
 
 See links:

diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn
index d5ebd7d93881741365c7dd4f6bd06a6cd7429b01..1c0cfc6f38279481c9175b2d3a87631c70c88eb6 100644 (file)
--- a/openpower/sv/sprs.mdwn
+++ b/openpower/sv/sprs.mdwn
@@ -1,20 +1,22 @@
-# CSRs <a name="csrs"></a>
+[[!tag standards]]
 
-There are five CSRs, available in any privilege level:
+# SPRs <a name="sprs"></a>
+
+There are five SPRs, available in any privilege level:
 
 * MVL (the Maximum Vector Length)
-* VL (which has different characteristics from standard CSRs)
+* VL (which has different characteristics from standard SPRs)
 * SUBVL (effectively a kind of SIMD)
 * STATE (containing copies of MVL, VL and SUBVL as well as context information)
 
-For Privilege Levels (trap handling) there are the following CSRs,
+For Privilege Levels (trap handling) there are the following SPRs,
 where x may be u, s or h for User, Supervisor or Hypervisor
 Modes respectively:
 
 * (x)eSTATE (useful for saving and restoring during context switch,
   and for providing fast transitions)
 
-The u/s CSRs are treated and handled exactly like their (x)epc
+The u/s SPRs are treated and handled exactly like their (x)epc
 equivalents.  On entry to or exit from a privilege level, the contents
 of its (x)eSTATE are swapped with STATE.
 
@@ -47,7 +49,7 @@ Illegal values raise an exception.
 
 ## STATE
 
-This is a standard CSR that contains sufficient information for a
+This is a standard SPR that contains sufficient information for a
 full context save/restore.  It contains (and permits setting of):
 
 * MVL
@@ -59,7 +61,7 @@ full context save/restore.  It contains (and permits setting of):
 * svoffs - the subvector element offset of the current
   parallel instruction being executed
 
-The format of the STATE CSR is as follows:
+The format of the STATE SPR is as follows:
 
 | Field | Name     | Description           |
 | ----- | -------- | --------------------- |

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index cfadc1a3de689a112357d75d5f8184edf7835002..8e2a8d098137f44c0578000f252910dbc78d2bd9 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # SVP64 for OpenPOWER ISA v3.0B
 
 This document describes [[SV|sv]] augmentation of the [[OpenPOWER|openpower]] v3.0B [[ISA|openpower/isa/]]. Permission to create commercial v3.1B implementations has not yet been granted through the issuance of a v3.1B EULA by the [[!wikipedia OpenPOWER_Foundation]] (only v3.0B)

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 6210310b172fa3e40d5facc7aa69881e3999f2b9..d9e401db7684cc6c9c0ef9f829cb48b774c49394 100644 (file)
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # SV Vector Operations.
 
 The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example.  This section includes such examples.  Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors)

diff --git a/openpower/sv/vector_swizzle.mdwn b/openpower/sv/vector_swizzle.mdwn
index 89984ffd27f740a6a63e3fd96a49da7908c80245..34322e8a4677a4674e8f0cd7f61a182893beced0 100644 (file)
--- a/openpower/sv/vector_swizzle.mdwn
+++ b/openpower/sv/vector_swizzle.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # SV Vector Prefix Swizzle
 
 * <https://bugs.libre-soc.org/show_bug.cgi?id=139>