Add another test

diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys
index 4b7716739b4c2ef52bee1a392a808a5baa48e744..bb908cbbffa8e19d8ccc471ce21cc09a5eaf542a 100644 (file)
--- a/tests/arch/xilinx/blockram.ys
+++ b/tests/arch/xilinx/blockram.ys
@@ -84,7 +84,14 @@ design -reset
 read_verilog ../common/blockram.v
 hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
 setattr -set ram_style "block" m:memory
-dump m:*
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/blockram.v
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
+setattr -set ram_block 1 m:memory
 synth_xilinx -top sync_ram_sdp
 cd sync_ram_sdp
 select -assert-count 1 t:RAMB18E1