[ARM] PR target/69857 Remove bogus early return false; in gen_operands_ldrd_strd

	PR target/69857
	* config/arm/arm.c (gen_operands_ldrd_strd): Remove bogus early
	return.  Reindent transformation comment and mention the ARM state
	behavior.

From-SVN: r236635

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4dc6e7de1a5d79c5df436038472215be92ec9b20..433493df5423962ca8b1f7582a66c9ee09a13977 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2016-05-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR target/69857
+       * config/arm/arm.c (gen_operands_ldrd_strd): Remove bogus early
+       return.  Reindent transformation comment and mention the ARM state
+       behavior.
+
 2016-05-24  Kugan Vivekanandarajah  <kuganv@linaro.org>
 
        PR middle-end/71252

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index af9725b93d4825d59c39e52019983fd784b5180f..a4f474baea8dd39cf732468d227041876c5f69cc 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -15982,14 +15982,17 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
   /* If the same input register is used in both stores
      when storing different constants, try to find a free register.
      For example, the code
-        mov r0, 0
-        str r0, [r2]
-        mov r0, 1
-        str r0, [r2, #4]
+       mov r0, 0
+       str r0, [r2]
+       mov r0, 1
+       str r0, [r2, #4]
      can be transformed into
-        mov r1, 0
-        strd r1, r0, [r2]
-     in Thumb mode assuming that r1 is free.  */
+       mov r1, 0
+       mov r0, 1
+       strd r1, r0, [r2]
+     in Thumb mode assuming that r1 is free.
+     For ARM mode do the same but only if the starting register
+     can be made to be even.  */
   if (const_store
       && REGNO (operands[0]) == REGNO (operands[1])
       && INTVAL (operands[4]) != INTVAL (operands[5]))
@@ -16008,7 +16011,6 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
       }
     else if (TARGET_ARM)
       {
-        return false;
         int regno = REGNO (operands[0]);
         if (!peep2_reg_dead_p (4, operands[0]))
           {