soc/add_sdram: add sdram csr

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 464e3f92c6c0f69bf0398540739f544b052958a5..d4820261e5dc2a862659dc4f2a427fa93c6920c1 100755 (executable)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -905,6 +905,7 @@ class LiteXSoC(SoC):
             timing_settings = module.timing_settings,
             clk_freq        = self.sys_clk_freq,
             **kwargs)
+        self.csr.add("sdram")
 
         # LiteDRAM port ----------------------------------------------------------------------------
         port = self.sdram.crossbar.get_port()

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index e68fbd1fea2a1b056d0b245f81bff5333a03d26d..e72116cdf07db8ff83a96ee6c48f561cb40c2fb7 100644 (file)
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -18,12 +18,6 @@ __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
 # SoCSDRAM -----------------------------------------------------------------------------------------
 
 class SoCSDRAM(SoCCore):
-    csr_map = {
-        "sdram":    8,
-        "l2_cache": 9,
-    }
-    csr_map.update(SoCCore.csr_map)
-
     def __init__(self, platform, clk_freq,
         l2_size           = 8192,
         l2_reverse        = True,