radeonsi: remove no-op 32-bit masking

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c
index 65339bbb66f8bd5f9de77e7dc81c73c3a910c45b..deeae0a6a65d87c4916762bc7e84a0db7b26a88b 100644 (file)
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -341,8 +341,8 @@ static void r600_emit_query_predication(struct r600_common_context *ctx, struct
        
                        while (results_base < qbuf->results_end) {
                                radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
-                               radeon_emit(cs, (va + results_base) & 0xFFFFFFFFUL);
-                               radeon_emit(cs, op | (((va + results_base) >> 32UL) & 0xFF));
+                               radeon_emit(cs, va + results_base);
+                               radeon_emit(cs, op | (((va + results_base) >> 32) & 0xFF));
                                r600_emit_reloc(ctx, &ctx->rings.gfx, qbuf->buf, RADEON_USAGE_READ,
                                                RADEON_PRIO_MIN);
                                results_base += query->result_size;

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index d4fe5653687a03b2fbefd35709b083dd97875cfb..0cdecd6da79005204060e5d77bc4c958e000bc53 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -362,7 +362,7 @@ static void si_launch_grid(
        shader_va += pc;
 #endif
        si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
-       si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff);
+       si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
        si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 
        si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1,

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 890be071596eb13ee6696f70469d499876bc54aa..b74c893c7d5d7ad37491461c73059175baecdaca 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -426,7 +426,7 @@ static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
                va = rbuffer->gpu_address + offset;
 
                /* Fill in T# buffer resource description */
-               desc[0] = va & 0xFFFFFFFF;
+               desc[0] = va;
                desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
                          S_008F04_STRIDE(vb->stride);
 

diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c
index 7a0076e7aa919087de1dffa72ef1563e0a109641..1a7eeaecf9e561f837c796d7690308c6d803c0d9 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -86,8 +86,8 @@ static void si_dma_copy_buffer(struct si_context *ctx,
        for (i = 0; i < ncopy; i++) {
                csize = size < max_csize ? size : max_csize;
                cs->buf[cs->cdw++] = SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, csize);
-               cs->buf[cs->cdw++] = dst_offset & 0xffffffff;
-               cs->buf[cs->cdw++] = src_offset & 0xffffffff;
+               cs->buf[cs->cdw++] = dst_offset;
+               cs->buf[cs->cdw++] = src_offset;
                cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff;
                cs->buf[cs->cdw++] = (src_offset >> 32UL) & 0xff;
                dst_offset += csize << shift;

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 98b42890f7d6fd19631dd9e9186d96cf1cfe2af2..ab5b3ee9ce90ebf01287cd3200f46a2e310f530f 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3781,7 +3781,7 @@ void si_shader_apply_scratch_relocs(struct si_context *sctx,
                        uint64_t scratch_va)
 {
        unsigned i;
-       uint32_t scratch_rsrc_dword0 = scratch_va & 0xffffffff;
+       uint32_t scratch_rsrc_dword0 = scratch_va;
        uint32_t scratch_rsrc_dword1 =
                S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
                |  S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64);