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Fix RSTP
author
Eddie Hung
<eddie@fpgeh.com>
Wed, 11 Sep 2019 03:56:13 +0000
(20:56 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Wed, 11 Sep 2019 03:56:13 +0000
(20:56 -0700)
passes/pmgen/xilinx_dsp.cc
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diff --git
a/passes/pmgen/xilinx_dsp.cc
b/passes/pmgen/xilinx_dsp.cc
index fe82b13075fd6e4bfcaf7463a0cc3cb9f230a445..055b3d6aaed98aef61d43cbff57fcddd0531008d 100644
(file)
--- a/
passes/pmgen/xilinx_dsp.cc
+++ b/
passes/pmgen/xilinx_dsp.cc
@@
-438,7
+438,7
@@
void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
st.ffPrstmux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
}
else
- cell->setPort("\\RSTP", State::S
1
);
+ cell->setPort("\\RSTP", State::S
0
);
if (st.ffPcemux) {
SigSpec S = st.ffPcemux->getPort("\\S");
cell->setPort("\\CEP", st.ffPcepol ? S : pm.module->Not(NEW_ID, S));