* config/bfin-parse.y (asm_1): Fix reduce/reduce conflicts.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3d023dfc38e443da192fe52455dce902ceddc1ab..eb8240d6f8bed6a16f4df11cff712cb03819cad6 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2008-09-26  Jie Zhang  <jie.zhang@analog.com>
+
+       * config/bfin-parse.y (asm_1): Fix reduce/reduce conflicts.
+
 2008-09-24  Richard Henderson  <rth@redhat.com>
 
        * dw2gencfi.c (DWARF2_ADDR_SIZE): Provide default.

diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y
index 283b8130fc3003da2ed115aa30936132a89becd0..f91224ed5dc365f6a685467d48a000a484a165df 100644 (file)
--- a/gas/config/bfin-parse.y
+++ b/gas/config/bfin-parse.y
@@ -1932,22 +1932,20 @@ asm_1:
          else
            return yyerror ("Bad shift value or register");
        }
-       | HALF_REG ASSIGN HALF_REG LESS_LESS expr
-       {
-         if (IS_UIMM ($5, 4))
-           {
-             notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
-             $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
-           }
-         else
-           return yyerror ("Bad shift value");
-       }
        | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod 
        {
          if (IS_UIMM ($5, 4))
            {
-             notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
-             $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
+             if ($6.s0)
+               {
+                 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
+                 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
+               }
+             else
+               {
+                 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
+                 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
+               }
            }
          else
            return yyerror ("Bad shift value");