// It seems like barriers are never required for tessellation since
// the warp size is 32, and there are always at most 32 tcs threads.
bb->remove(i);
+ } else
+ if (i->op == OP_LOAD && i->subOp == NV50_IR_SUBOP_LDC_IS) {
+ int offset = i->src(0).get()->reg.data.offset;
+ if (abs(offset) > 0x10000)
+ i->src(0).get()->reg.fileIndex += offset >> 16;
+ i->src(0).get()->reg.data.offset = (int)(short)offset;
} else {
// TODO: Move this to before register allocation for operations that
// need the $c register !
virtual bool insnCanLoad(const Instruction *insn, int s,
const Instruction *ld) const = 0;
virtual bool insnCanLoadOffset(const Instruction *insn, int s,
- int offset) const { return true; }
+ int offset) const = 0;
virtual bool isOpSupported(operation, DataType) const = 0;
virtual bool isAccessSupported(DataFile, DataType) const = 0;
virtual bool isModSupported(const Instruction *,
return true;
}
+bool
+TargetNVC0::insnCanLoadOffset(const Instruction *insn, int s, int offset) const
+{
+ const ValueRef& ref = insn->src(s);
+ if (ref.getFile() == FILE_MEMORY_CONST &&
+ (insn->op != OP_LOAD || insn->subOp != NV50_IR_SUBOP_LDC_IS))
+ return offset >= -0x8000 && offset < 0x8000;
+ return true;
+}
+
bool
TargetNVC0::isAccessSupported(DataFile file, DataType ty) const
{
virtual bool insnCanLoad(const Instruction *insn, int s,
const Instruction *ld) const;
+ virtual bool insnCanLoadOffset(const Instruction *insn, int s,
+ int offset) const;
virtual bool isOpSupported(operation, DataType) const;
virtual bool isAccessSupported(DataFile, DataType) const;
virtual bool isModSupported(const Instruction *, int s, Modifier) const;