2012-10-04 Chao-ying Fu <fu@mips.com>

	    Steve Ellcey  <sellcey@mips.com>

	* mips/mips3264r2.igen (rdhwr): New.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 95e23dea9e4bb9a2b2c23985409d1909e8d1c48e..4d5bde28da5725e723b29e19ae4e8c2402cded1a 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,8 @@
+2012-10-04  Chao-ying Fu  <fu@mips.com>
+           Steve Ellcey  <sellcey@mips.com>
+
+       * mips/mips3264r2.igen (rdhwr): New.
+
 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
 
        * configure.ac: Always link against dv-sockser.o.

diff --git a/sim/mips/mips3264r2.igen b/sim/mips/mips3264r2.igen
index c52ec3b2c4ff63fdeacf488c610be2661f8b9d69..e0b6d5bf6406b3dfb21e832c8727ecaf234a678f 100644 (file)
--- a/sim/mips/mips3264r2.igen
+++ b/sim/mips/mips3264r2.igen
@@ -241,6 +241,17 @@
 }
 
 
+011111,00000,5.RT,5.RD,00000,111011::32::RDHWR
+"rdhwr r<RT>, r<RD>"
+*mips32r2:
+*mips64r2:
+{
+  // Return 0 for all hardware registers currently
+  GPR[RT] = EXTEND32 (0);
+  TRACE_ALU_RESULT1 (GPR[RT]);
+}
+
+
 011111,00000,5.RT,5.RD,00010,100000::32::WSBH
 "wsbh r<RD>, r<RT>"
 *mips32r2: