global: pep8 (E231)

diff --git a/mibuild/altera/quartus.py b/mibuild/altera/quartus.py
index 06f17528544d7fb4192d49441d4d7d9ad9fe0fa1..02da446b83072b5e86980dbafe9da41b4c969321 100644 (file)
--- a/mibuild/altera/quartus.py
+++ b/mibuild/altera/quartus.py
@@ -50,10 +50,10 @@ def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name):
         # Enforce use of SystemVerilog (Quartus does not support global parameters in Verilog)
         if language == "verilog":
             language = "systemverilog"
-        qsf_contents += "set_global_assignment -name "+language.upper()+"_FILE " + filename.replace("\\","/") + "\n"
+        qsf_contents += "set_global_assignment -name "+ language.upper() + "_FILE " + filename.replace("\\", "/") + "\n"
 
     for path in vincpaths:
-        qsf_contents += "set_global_assignment -name SEARCH_PATH " + path.replace("\\","/") + "\n"
+        qsf_contents += "set_global_assignment -name SEARCH_PATH " + path.replace("\\", "/") + "\n"
 
     qsf_contents += _build_qsf(named_sc, named_pc)
     qsf_contents += "set_global_assignment -name DEVICE " + device

diff --git a/mibuild/platforms/de0nano.py b/mibuild/platforms/de0nano.py
index eec8fd28410d4b65dacc7e7b1c4e8e0789b4618e..7e6d47b20066948bacea244c3d48b9e2175d1a7a 100644 (file)
--- a/mibuild/platforms/de0nano.py
+++ b/mibuild/platforms/de0nano.py
@@ -40,7 +40,7 @@ _io = [
         Subsignal("cas_n", Pins("L1")),
         Subsignal("we_n", Pins("C2")),
         Subsignal("dq", Pins("G2 G1 L8 K5 K2 J2 J1 R7 T4 T2 T3 R3 R5 P3 N3 K1")),
-        Subsignal("dm", Pins("R6","T5")),
+        Subsignal("dm", Pins("R6 T5")),
         IOStandard("3.3-V LVTTL")
     ),
 

diff --git a/mibuild/sim/verilator.py b/mibuild/sim/verilator.py
index e0d7ff33bcd5221efc83b4548f6eb3e2db412efc..cc7313c8557bff3e3194bd36072e8800cd0f0532 100644 (file)
--- a/mibuild/sim/verilator.py
+++ b/mibuild/sim/verilator.py
@@ -100,7 +100,7 @@ make -j -C obj_dir/ -f Vdut.mk Vdut
     build_script_file = "build_" + build_name + ".sh"
     tools.write_to_file(build_script_file, build_script_contents, force_unix=True)
 
-    _build_tb(platform, vns, serial, os.path.join("..", sim_path,"dut_tb.cpp"))
+    _build_tb(platform, vns, serial, os.path.join("..", sim_path, "dut_tb.cpp"))
     if verbose:
         r = subprocess.call(["bash", build_script_file])
     else:

diff --git a/migen/fhdl/edif.py b/migen/fhdl/edif.py
index 8222bd68add0a8d3af12e9a06c6e825343e4e01f..32c3cf9f5d5a5c03f5da3ce5f9adafef769685df 100644 (file)
--- a/migen/fhdl/edif.py
+++ b/migen/fhdl/edif.py
@@ -137,7 +137,7 @@ def _generate_cells(f):
     return [_Cell(k, v) for k, v in cell_dict.items()]
 
 
-def _generate_instances(f,ns):
+def _generate_instances(f, ns):
     instances = []
     for special in f.specials:
         if isinstance(special, Instance):

diff --git a/migen/genlib/roundrobin.py b/migen/genlib/roundrobin.py
index 2d28b8a4a88a82266f868f9f9ff668f5e2399844..5dd56759d8f444cfa224fc5c0f3d4b27a8afed5a 100644 (file)
--- a/migen/genlib/roundrobin.py
+++ b/migen/genlib/roundrobin.py
@@ -17,7 +17,7 @@ class RoundRobin(Module):
             cases = {}
             for i in range(n):
                 switch = []
-                for j in reversed(range(i+1,i+n)):
+                for j in reversed(range(i+1, i+n)):
                     t = j % n
                     switch = [
                         If(self.request[t],