hdl.mem: cast reset value for transparent read ports to integer.

diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py
index d34c5f02e7bdc1e06a253ee28ab14ebdb7be1ff3..5b016ab85d6b7373541595cac6fbf6c7312843dc 100644 (file)
--- a/nmigen/hdl/mem.py
+++ b/nmigen/hdl/mem.py
@@ -145,7 +145,7 @@ class ReadPort(Elaboratable):
             # value of the data output is forcibly set to the 0th initial value, if any--note that
             # many FPGAs do not guarantee this behavior!
             if len(self.memory.init) > 0:
-                self.data.reset = self.memory.init[0]
+                self.data.reset = operator.index(self.memory.init[0])
             latch_addr = Signal.like(self.addr)
             f.add_statements(
                 latch_addr.eq(self.addr),