soc/cores/clock: add CycloneVPLL.

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index ed4161cf0cffa47112686be01b943f2767f6a498..a149cdcaee4b20969eaf8011b82cf563c0dd76b7 100644 (file)
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -815,9 +815,44 @@ class CycloneIVPLL(AlteraClocking):
             "-9L": (5e6, 256e6),
         }[speedgrade]
         self.clko_freq_range = {
-            "-6" : (0, 472.5e6),
-            "-7" : (0, 450e6),
-            "-8" : (0, 402.5e6),
-            "-8L": (0, 362e6),
-            "-9L": (0, 265e6),
+            "-6" : (0e6, 472.5e6),
+            "-7" : (0e6, 450e6),
+            "-8" : (0e6, 402.5e6),
+            "-8L": (0e6, 362e6),
+            "-9L": (0e6, 265e6),
+        }[speedgrade]
+
+# Altera / CycloneV --------------------------------------------------------------------------------
+
+class CycloneVPLL(AlteraClocking):
+    nclkouts_max   = 5
+    n_div_range    = (1, 512+1)
+    m_div_range    = (1, 512+1)
+    c_div_range    = (1, 512+1)
+    clkin_pfd_freq_range  = (5e6, 325e6)  # FIXME: use
+    clkfin_pfd_freq_range = (50e6, 160e6) # FIXME: use
+    def __init__(self, speedgrade="-C6"):
+        self.logger = logging.getLogger("CycloneIVPLL")
+        self.logger.info("Creating CycloneIVPLL, {}.".format(colorer("speedgrade {}".format(speedgrade))))
+        AlteraClocking.__init__(self)
+        self.clkin_freq_range = {
+            "-C6" : (5e6, 670e6),
+            "-C7" : (5e6, 622e6),
+            "-I7" : (5e6, 622e6),
+            "-C8" : (5e6, 622e6),
+            "-A7" : (5e6, 500e6),
+        }[speedgrade]
+        self.vco_freq_range = {
+            "-C6" : (5e6, 1600e6),
+            "-C7" : (5e6, 1600e6),
+            "-I7" : (5e6, 1600e6),
+            "-C8" : (5e6, 1300e6),
+            "-A7" : (5e6, 1300e6),
+        }[speedgrade]
+        self.clko_freq_range = {
+            "-C6" : (0e6, 550e6),
+            "-C7" : (0e6, 550e6),
+            "-I7" : (0e6, 550e6),
+            "-C8" : (0e6, 460e6),
+            "-A7" : (0e6, 460e6),
         }[speedgrade]

diff --git a/test/test_clock.py b/test/test_clock.py
index 9762da7c8075d6943626d2633f99b36e96fa405b..0c3d78a03e1a66d755bef0e98b97ecf5f7f16bca 100644 (file)
--- a/test/test_clock.py
+++ b/test/test_clock.py
@@ -75,3 +75,11 @@ class TestClock(unittest.TestCase):
         for i in range(pll.nclkouts_max):
             pll.create_clkout(ClockDomain("clkout{}".format(i)), 100e6)
         pll.compute_config()
+
+    # Altera / CycloneV
+    def test_cyclonevpll(self):
+        pll = CycloneVPLL()
+        pll.register_clkin(Signal(), 50e6)
+        for i in range(pll.nclkouts_max):
+            pll.create_clkout(ClockDomain("clkout{}".format(i)), 100e6)
+        pll.compute_config()