[AArch64] Add vector fix, fixuns, fix_trunc, fixuns_trunc standard patterns

gcc/
	* config/aarch64/aarch64-simd.md
	(<optab><VDQF:mode><fcvt_target>2): New, maps to fix, fixuns.
	(<fix_trunc_optab><VDQF:mode><fcvt_target>2): New, maps to
	fix_trunc, fixuns_trunc.
	(ftrunc<VDQF:mode>2): New.
	* config/aarch64/iterators.md (optab): Add fix, fixuns.
	(fix_trunc_optab): New.

From-SVN: r198403

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bef76a82856b4dbefa9720a6c4d0303080b9a021..3c42d606ae2b694baacd4c37d27e028be02044c4 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2013-04-29  James Greenhalgh  <james.greenhalgh@arm.com>
+
+       * config/aarch64/aarch64-simd.md
+       (<optab><VDQF:mode><fcvt_target>2): New, maps to fix, fixuns.
+       (<fix_trunc_optab><VDQF:mode><fcvt_target>2): New, maps to
+       fix_trunc, fixuns_trunc.
+       (ftrunc<VDQF:mode>2): New.
+       * config/aarch64/iterators.md (optab): Add fix, fixuns.
+       (fix_trunc_optab): New.
+
 2013-04-29  James Greenhalgh  <james.greenhalgh@arm.com>
 
        * config/aarch64/aarch64-builtins.c

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 454609476634e6a352e9be5dedd4e7b4c90d44a2..32ea587a0ac41002612c2b172229296772ab14b7 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1257,6 +1257,29 @@
    (set_attr "simd_mode" "<MODE>")]
 )
 
+(define_expand "<optab><VDQF:mode><fcvt_target>2"
+  [(set (match_operand:<FCVT_TARGET> 0 "register_operand")
+       (FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET>
+                              [(match_operand:VDQF 1 "register_operand")]
+                              UNSPEC_FRINTZ)))]
+  "TARGET_SIMD"
+  {})
+
+(define_expand "<fix_trunc_optab><VDQF:mode><fcvt_target>2"
+  [(set (match_operand:<FCVT_TARGET> 0 "register_operand")
+       (FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET>
+                              [(match_operand:VDQF 1 "register_operand")]
+                              UNSPEC_FRINTZ)))]
+  "TARGET_SIMD"
+  {})
+
+(define_expand "ftrunc<VDQF:mode>2"
+  [(set (match_operand:VDQF 0 "register_operand")
+       (unspec:VDQF [(match_operand:VDQF 1 "register_operand")]
+                     UNSPEC_FRINTZ))]
+  "TARGET_SIMD"
+  {})
+
 (define_insn "<optab><fcvt_target><VDQF:mode>2"
   [(set (match_operand:VDQF 0 "register_operand" "=w")
        (FLOATUORS:VDQF

diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 8668d3f631a7bd980d600c98436995c05ffef6fa..d774c4c8cbc318a86f45bb7fa35b92576f57d3ba 100644 (file)
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -560,6 +560,8 @@
                         (zero_extend "zero_extend")
                         (sign_extract "extv")
                         (zero_extract "extzv")
+                        (fix "fix")
+                        (unsigned_fix "fixuns")
                         (float "float")
                         (unsigned_float "floatuns")
                         (and "and")
@@ -580,6 +582,9 @@
                         (lt "lt")
                         (ge "ge")])
 
+(define_code_attr fix_trunc_optab [(fix "fix_trunc")
+                                  (unsigned_fix "fixuns_trunc")])
+
 ;; Optab prefix for sign/zero-extending operations
 (define_code_attr su_optab [(sign_extend "") (zero_extend "u")
                            (div "") (udiv "u")