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diff --git a/180nm_Oct2020.mdwn b/180nm_Oct2020.mdwn
index 27417ece899f278fc312d381a2bc65cc942144e7..e1f29df14fe5b93e6ee01c6f9d904b4d8791952b 100644 (file)
--- a/180nm_Oct2020.mdwn
+++ b/180nm_Oct2020.mdwn
@@ -19,7 +19,7 @@ To be expanded with links to bugreports
 * a very very basic Common Data Bus infrastructure.
 * a TLB and MMU are not strictly essential (not for a proof-of-concept ASIC)
 * neither in some ways is a L1 cache
-* [[180nm_oct2020/interfaces]] we need as a bare minimum include GPIO, EINT, SPI and QSPI,
+* [[180nm_Oct2020/interfaces]] we need as a bare minimum include GPIO, EINT, SPI and QSPI,
   I2C, UART16550, LPC (from Raptor Engineering) and that actually might
   even be it.