mem: Add checks to sendTimingReq in cache

A small fix to ensure the return value is not ignored.

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index a792de19d635fea1ad59a5a4d6533830d268519f..8c091fa3978d3b5eb3313399f7a06202fc240154 100644 (file)
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -462,7 +462,9 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
 
     // Just forward the packet if caches are disabled.
     if (system->bypassCaches()) {
-        memSidePort->sendTimingReq(pkt);
+        // @todo This should really enqueue the packet rather
+        bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt);
+        assert(success);
         return true;
     }
 
@@ -483,7 +485,10 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
             snoopPkt->busFirstWordDelay = snoopPkt->busLastWordDelay = 0;
             snoopPkt->setExpressSnoop();
             snoopPkt->assertMemInhibit();
-            memSidePort->sendTimingReq(snoopPkt);
+            bool M5_VAR_USED success = memSidePort->sendTimingReq(snoopPkt);
+            // the packet is marked inhibited and will thus bypass any
+            // flow control
+            assert(success);
             // main memory will delete snoopPkt
         }
         // since we're the official target but we aren't responding,