ok this is tricky: an extra parameter has to be passed into sv_insn_t::remap

the reason is that the remap has to know if the register being
remapped is an int or a float.  the place where that is known
is at *decode* time... and that means that id_regs.py has to
look that up and pass it on (in a #define REGS_PATTERN).
the reason it is passed in as a pattern is so that svn_insn_t rd/rs1-3
have access to the information that is needed

diff --git a/id_regs.py b/id_regs.py
index 830ef95f7c405d6d8ac01e96368642c1889b4566..b40e5cedab29c6ed0b1b4cafebf45a52e5a29b75 100644 (file)
--- a/id_regs.py
+++ b/id_regs.py
@@ -39,11 +39,13 @@ def list_insns():
         res.append((os.path.join(insns_dir, fname), insn))
     return res
 
-patterns = ['WRITE_RD', 'RS1', 'RS2', 'RS3',
-            'WRITE_FRD', 'FRS1', 'FRS2', 'FRS3']
+intpatterns = ['WRITE_RD', 'RS1', 'RS2', 'RS3']
+floatpatterns = ['WRITE_FRD', 'FRS1', 'FRS2', 'FRS3']
+patterns = intpatterns + floatpatterns
 
 def find_registers(fname):
     res = []
+    isintfloat = 0x0 + 0xf << 4
     with open(fname) as f:
         f = f.read()
         for pattern in patterns:
@@ -57,9 +59,17 @@ def find_registers(fname):
             p = pattern
             if p.startswith('WRITE_'):
                 p = p[6:]
+            if pattern in intpatterns:
+                idx = intpatterns.index(pattern)
+                isintfloat += 1 << idx
+            if pattern in floatpatterns:
+                idx = floatpatterns.index(pattern)
+                isintfloat &= ~(1 << (idx+4))
             res.append('#define USING_REG_%s' % p)
     if not res:
-        return '#define USING_NOREGS'
+        return '#define USING_NOREGS\n' \
+               '#define REGS_PATTERN 0x0\n'
+    res.append('#define REGS_PATTERN 0x%x' % isintfloat)
     return '\n'.join(res)
 
 if __name__ == '__main__':

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 4199de033fe893d18a576b44af299d9b1cc1e4ab..222cde20c9028d212c0add9d008e7ca6025f1148 100644 (file)
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -13,7 +13,10 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
 #ifndef USING_NOREGS
   int voffs = 0;
   int vlen = 1;
-  sv_insn_t insn(bits, voffs);
+  // need to know if register is used as float or int.
+  // REGS_PATTERN is generated by id_regs.py (per opcode)
+  unsigned int floatintmap = REGS_PATTERN;
+  sv_insn_t insn(bits, voffs, floatintmap);
   bool vectorop = false;
   reg_t predicate = 0;
   // identify which regs have had their CSR entries set as vectorised.

diff --git a/riscv/sv.cc b/riscv/sv.cc
index ad6b0e070b2b67a64026383b10788f9be07c2f27..b0b65ee45001a461c14025de78b2e2c8a2a3d694 100644 (file)
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -29,7 +29,7 @@ bool sv_check_reg(bool intreg, uint64_t reg)
   return false;
 }
 
-uint64_t sv_insn_t::remap(uint64_t reg)
+uint64_t sv_insn_t::remap(uint64_t reg, bool isint)
 {
     return reg;
 }

diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index a92661027d2a620a58c230ddaf191c3e1f436f6c..7faf48a155d069b0b93976f3b34f9490083bb744 100644 (file)
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -6,19 +6,26 @@
 #include "sv.h"
 #include "decode.h"
 
+#define REG_RD 0x1
+#define REG_RS1 0x2
+#define REG_RS2 0x4
+#define REG_RS3 0x8
+
 class sv_insn_t: public insn_t
 {
 public:
-  sv_insn_t(insn_bits_t bits, int& v) : insn_t(bits), voffs(v) {}
-  uint64_t rd () { return remap(insn_t::rd()); }
-  uint64_t rs1() { return remap(insn_t::rs1()); }
-  uint64_t rs2() { return remap(insn_t::rs2()); }
-  uint64_t rs3() { return remap(insn_t::rs3()); }
+  sv_insn_t(insn_bits_t bits, int& v, unsigned int f) :
+            insn_t(bits), voffs(v), fimap(f) {}
+  uint64_t rd () { return remap(insn_t::rd (), fimap & REG_RD); }
+  uint64_t rs1() { return remap(insn_t::rs1(), fimap & REG_RS1); }
+  uint64_t rs2() { return remap(insn_t::rs2(), fimap & REG_RS2); }
+  uint64_t rs3() { return remap(insn_t::rs3(), fimap & REG_RS3); }
 private:
   int &voffs;
+  unsigned int fimap;
   // remaps the register through the lookup table.
   // will need to take the current loop index/offset somehow
-  uint64_t remap(uint64_t reg);
+  uint64_t remap(uint64_t reg, bool isint);
 };
 
 #endif