}
}
- // Connect $currQ as an input to the flop box
+ // Connect <cell>.$currQ (inserted by abc9_map.v) as an input to the flop box
if (box_module->get_bool_attribute("\\abc9_flop")) {
- IdString port_name = "\\$currQ";
- Wire *w = box_module->wire(port_name);
- if (!w)
- log_error("'$currQ' is not a wire present in module '%s'.\n", log_id(box_module));
SigSpec rhs = module->wire(stringf("%s.$currQ", cell->name.c_str()));
if (rhs.empty())
log_error("'%s.$currQ' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
- log_assert(GetSize(w) == GetSize(rhs));
int offset = 0;
for (auto b : rhs) {
else
alias_map[b] = I;
}
- co_bits.emplace_back(b, cell, port_name, offset++, 0);
+ co_bits.emplace_back(b, cell, "\\$currQ", offset++, 0);
unused_bits.erase(b);
}
}
log_assert(box_module);
IdString derived_name = box_module->derive(module->design, cell->parameters);
box_module = module->design->module(derived_name);
+ if (box_module->has_processes())
+ Pass::call_on_module(module->design, box_module, "proc");
int box_inputs = 0, box_outputs = 0;
auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);
RTLIL::Wire *holes_wire;
- RTLIL::SigSpec port_wire;
+ RTLIL::SigSpec port_sig;
if (w->port_input)
for (int i = 0; i < GetSize(w); i++) {
box_inputs++;
holes_module->ports.push_back(holes_wire->name);
}
if (holes_cell)
- port_wire.append(holes_wire);
+ port_sig.append(holes_wire);
}
if (w->port_output) {
box_outputs += GetSize(w);
holes_wire->port_output = true;
holes_wire->port_id = port_id++;
holes_module->ports.push_back(holes_wire->name);
- if (holes_cell)
- port_wire.append(holes_wire);
+ if (holes_cell) {
+ port_sig.append(holes_wire);
+ }
else
holes_module->connect(holes_wire, State::S0);
}
}
- if (!port_wire.empty()) {
+ if (!port_sig.empty()) {
if (r.second)
- holes_cell->setPort(w->name, port_wire);
+ holes_cell->setPort(w->name, port_sig);
else
- holes_module->connect(port_wire, holes_cell->getPort(w->name));
+ holes_module->connect(holes_cell->getPort(w->name), port_sig);
}
}
- // For flops only, create an extra input for $currQ
+ // For flops only, create an extra 1-bit input that drives a new wire
+ // called "<cell>.$currQ" that is used below
if (box_module->get_bool_attribute("\\abc9_flop")) {
log_assert(holes_cell);
- Wire *w = box_module->wire("\\$currQ");
- Wire *holes_wire;
- RTLIL::SigSpec port_wire;
- for (int i = 0; i < GetSize(w); i++) {
- box_inputs++;
- holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
- if (!holes_wire) {
- holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
- holes_wire->port_input = true;
- holes_wire->port_id = port_id++;
- holes_module->ports.push_back(holes_wire->name);
- }
- port_wire.append(holes_wire);
+ box_inputs++;
+ Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
+ if (!holes_wire) {
+ holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
+ holes_wire->port_input = true;
+ holes_wire->port_id = port_id++;
+ holes_module->ports.push_back(holes_wire->name);
}
- w = holes_module->addWire(stringf("%s.$currQ", cell->name.c_str()), GetSize(w));
- w->set_bool_attribute("\\hierconn");
- holes_module->connect(w, port_wire);
+ Wire *w = holes_module->addWire(stringf("%s.$currQ", cell->name.c_str()));
+ holes_module->connect(w, holes_wire);
}
write_h_buffer(box_inputs);
//holes_module->fixup_ports();
holes_module->check();
- Design *design = holes_module->design;
- design->selection_stack.emplace_back(false);
- RTLIL::Selection& sel = design->selection_stack.back();
- log_assert(design->selected_active_module == module->name.c_str());
- design->selected_active_module = holes_module->name.str();
- sel.select(holes_module);
-
- Pass::call(design, "flatten -wb");
-
// TODO: Should techmap/aigmap/check all lib_whitebox-es just once,
// instead of per write_xaiger call
- Pass::call(design, "techmap");
- Pass::call(design, "aigmap");
- for (auto cell : holes_module->cells())
- if (!cell->type.in("$_NOT_", "$_AND_"))
+ Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap");
+
+ dict<SigBit, Wire*> output_port;
+ SigMap holes_sigmap(holes_module);
+ for (auto port_name : holes_module->ports) {
+ Wire *port = holes_module->wire(port_name);
+ if (port->port_input)
+ continue;
+ output_port.insert(std::make_pair(holes_sigmap(port), port));
+ }
+
+ dict<SigSig, SigSig> replace;
+ for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
+ auto cell = it->second;
+ if (cell->type.in("$_DFF_N_", "$_DFF_P_")) {
+ SigBit D = cell->getPort("\\D");
+ SigBit Q = cell->getPort("\\Q");
+ // Remove the DFF cell from what needs to be a combinatorial box
+ it = holes_module->cells_.erase(it);
+ Wire *port = output_port.at(Q);
+ log_assert(port);
+ // Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
+ // in order to extract the combinatorial control logic that feeds the box
+ // (i.e. clock enable, synchronous reset, etc.)
+ replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
+ // Since `flatten` above would have created wires named "<cell>.Q",
+ // extract the pre-techmap cell name
+ auto pos = Q.wire->name.str().rfind(".");
+ log_assert(pos != std::string::npos);
+ IdString driver = Q.wire->name.substr(0, pos);
+ // And drive the signal that was previously driven by "DFF.Q" (typically
+ // used to implement clock-enable functionality) with the "<cell>.$currQ"
+ // wire (which itself is driven an input port) we inserted above
+ Wire *currQ = holes_module->wire(stringf("%s.$currQ", driver.c_str()));
+ log_assert(currQ);
+ holes_module->connect(Q, currQ);
+ continue;
+ }
+ else if (!cell->type.in("$_NOT_", "$_AND_"))
log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
+ ++it;
+ }
- design->selection_stack.pop_back();
- design->selected_active_module = module->name.str();
+ for (auto &conn : holes_module->connections_) {
+ auto it = replace.find(conn);
+ if (it != replace.end())
+ conn = it->second;
+ }
// Move into a new (temporary) design so that "clean" will only
// operate (and run checks on) this one module
RTLIL::Design *holes_design = new RTLIL::Design;
- design->modules_.erase(holes_module->name);
+ module->design->modules_.erase(holes_module->name);
holes_design->add(holes_module);
Pass::call(holes_design, "clean -purge");
std::stringstream a_buffer;
XAigerWriter writer(holes_module, false /*zinit_mode*/, true /* holes_mode */);
writer.write_aiger(a_buffer, false /*ascii_mode*/);
-
delete holes_design;
f << "a";
if (!inst_module || !inst_module->attributes.count("\\abc9_flop"))
continue;
- auto derived_name = inst_module->derive(design, cell->parameters);
- auto derived_module = design->module(derived_name);
- log_assert(derived_module);
- if (derived_module->has_processes())
- Pass::call_on_module(design, derived_module, "proc");
- SigMap derived_sigmap(derived_module);
-
- SigSpec pattern;
- SigSpec with;
- for (auto &conn : cell->connections()) {
- Wire *first = derived_module->wire(conn.first);
- log_assert(first);
- SigSpec second = assign_map(conn.second);
- log_assert(GetSize(first) == GetSize(second));
- pattern.append(first);
- with.append(second);
- }
-
- Wire *abc9_clock_wire = derived_module->wire("\\$abc9_clock");
+ Wire *abc9_clock_wire = module->wire(stringf("%s.$abc9_clock", cell->name.c_str()));
if (abc9_clock_wire == NULL)
- log_error("'\\$abc9_clock' is not a wire present in module '%s'.\n", log_id(cell->type));
- SigSpec abc9_clock = derived_sigmap(abc9_clock_wire);
- abc9_clock.replace(pattern, with);
- for (const auto &c : abc9_clock.chunks())
- log_assert(!c.wire || c.wire->module == module);
+ log_error("'%s$abc9_clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+ SigSpec abc9_clock = assign_map(abc9_clock_wire);
- Wire *abc9_control_wire = derived_module->wire("\\$abc9_control");
+ Wire *abc9_control_wire = module->wire(stringf("%s.$abc9_control", cell->name.c_str()));
if (abc9_control_wire == NULL)
- log_error("'\\$abc9_control' is not a wire present in module '%s'.\n", log_id(cell->type));
- SigSpec abc9_control = derived_sigmap(abc9_control_wire);
- abc9_control.replace(pattern, with);
- for (const auto &c : abc9_control.chunks())
- log_assert(!c.wire || c.wire->module == module);
+ log_error("'%s$abc9_control' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+ SigSpec abc9_control = assign_map(abc9_control_wire);
unassigned_cells.erase(cell);
expand_queue.insert(cell);
) _TECHMAP_REPLACE_ (
.D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
);
- wire _TECHMAP_REPLACE_.$currQ = Q;
+ // `abc9' requires that complex flops be split into a combinatorial box
+ // feeding a simple flop ($_ABC9_FF_).
+ // Yosys will automatically analyse the simulation model (described in
+ // cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in
+ // order to extract the combinatorial control logic left behind.
+ // Specifically, a simulation model similar to the one below:
+ //
+ // ++===================================++
+ // || Sim model ||
+ // || /\/\/\/\ ||
+ // D -->>-----< > +------+ ||
+ // R -->>-----< Comb. > |$_DFF_| ||
+ // CE -->>-----< logic >-----| [NP]_|---+---->>-- Q
+ // || +--< > +------+ | ||
+ // || | \/\/\/\/ | ||
+ // || | | ||
+ // || +----------------------------+ ||
+ // || ||
+ // ++===================================++
+ //
+ // is transformed into:
+ //
+ // ++==================++
+ // || Comb box ||
+ // || ||
+ // || /\/\/\/\ ||
+ // D -->>-----< > || +------+
+ // R -->>-----< Comb. > || |$_ABC_|
+ // CE -->>-----< logic >--->>-- $nextQ --| FF_ |--+-->> Q
+ // $currQ +-->>-----< > || +------+ |
+ // | || \/\/\/\/ || |
+ // | || || |
+ // | ++==================++ |
+ // | |
+ // +----------------------------------------------+
\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+ // Special signal indicating control domain
+ // (which, combined with this cell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
+ // Special signal indicating the current value of the flip-flop
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+ wire _TECHMAP_REPLACE_.$currQ = Q;
endmodule
module FDRE_1 (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
) _TECHMAP_REPLACE_ (
.D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
);
- wire _TECHMAP_REPLACE_.$currQ = Q;
\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
+ // Special signal indicating the current value of the flip-flop
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+ wire _TECHMAP_REPLACE_.$currQ = Q;
endmodule
module FDCE (output reg Q, input C, CE, D, CLR);
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
- wire $currQ, $nextQ;
+ wire $nextQ, $currQ;
FDCE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_CLR_INVERTED(IS_CLR_INVERTED)
) _TECHMAP_REPLACE_ (
- .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(IS_CLR_INVERTED)
+ // ^^^ Note that async
+ // control is disabled
+ // and captured by
+ // $__ABC9_ASYNC below
);
- wire _TECHMAP_REPLACE_.$currQ = Q;
\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
- \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
+ // Since this is an async flop, async behaviour is also dealt with
+ // using the $_ABC9_ASYNC box by abc9_map.v
+ \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
+ // Special signal indicating the current value of the flip-flop
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+ wire _TECHMAP_REPLACE_.$currQ = $currQ;
endmodule
module FDCE_1 (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
FDCE_1 #(
.INIT(INIT)
) _TECHMAP_REPLACE_ (
- .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(1'b0)
+ // ^^^ Note that async
+ // control is disabled
+ // and captured by
+ // $__ABC9_ASYNC below
);
- wire _TECHMAP_REPLACE_.$currQ = Q;
\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
- \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
+ \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
+ // Special signal indicating the current value of the flip-flop
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+ wire _TECHMAP_REPLACE_.$currQ = $currQ;
endmodule
module FDPE (output reg Q, input C, CE, D, PRE);
.IS_D_INVERTED(IS_D_INVERTED),
.IS_PRE_INVERTED(IS_PRE_INVERTED),
) _TECHMAP_REPLACE_ (
- .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(IS_PRE_INVERTED)
+ // ^^^ Note that async
+ // control is disabled
+ // and captured by
+ // $__ABC9_ASYNC below
);
- wire _TECHMAP_REPLACE_.$currQ = Q;
\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
- \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
+ \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
+ // Special signal indicating the current value of the flip-flop
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+ wire _TECHMAP_REPLACE_.$currQ = $currQ;
endmodule
module FDPE_1 (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b0;
FDPE_1 #(
.INIT(INIT)
) _TECHMAP_REPLACE_ (
- .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(1'b0)
+ // ^^^ Note that async
+ // control is disabled
+ // and captured by
+ // $__ABC9_ASYNC below
);
- wire _TECHMAP_REPLACE_.$currQ = Q;
\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
- \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
+ \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
+ // Special signal indicating the current value of the flip-flop
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+ wire _TECHMAP_REPLACE_.$currQ = $currQ;
endmodule
module FDSE (output reg Q, input C, CE, D, S);
) _TECHMAP_REPLACE_ (
.D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
);
- wire _TECHMAP_REPLACE_.$currQ = Q;
\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
+ // Special signal indicating the current value of the flip-flop
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+ wire _TECHMAP_REPLACE_.$currQ = Q;
endmodule
module FDSE_1 (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b0;
) _TECHMAP_REPLACE_ (
.D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
);
- wire _TECHMAP_REPLACE_.$currQ = Q;
\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
+ // Special signal indicating the current value of the flip-flop
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+ wire _TECHMAP_REPLACE_.$currQ = Q;
endmodule
module RAM32X1D (
: (S0 ? I1 : I0);
endmodule
-module \$__ABC_FF_ (input D, output Q);
-endmodule
-
(* abc_box_id = 1000 *)
-module \$__ABC_ASYNC (input A, S, output Y);
+module \$__ABC9_ASYNC (input A, S, output Y);
endmodule
// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
# Box to emulate async behaviour of FD[CP]*
# Inputs: A S
# Outputs: Y
-$__ABC_ASYNC 1000 0 2 1
+$__ABC9_ASYNC 1000 0 2 1
0 764
# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
initial Q <= INIT;
- wire \$currQ ;
- reg \$nextQ ;
- always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
-`ifdef _ABC9
- // `abc9' requires that complex flops be split into a combinatorial
- // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
- // In order to achieve clock-enable behaviour, the current value
- // of the sequential output is required which Yosys will
- // connect to the special `$currQ' wire.
-
- // Special signal indicating clock domain
- // (used to partition the module so that `abc9' only performs
- // sequential synthesis (reachability analysis) correctly on
- // one domain at a time)
- wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
- // Special signal indicating control domain
- // (which, combined with this spell type, encodes to `abc9'
- // which flops may be merged together)
- wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
- always @* Q = \$nextQ ;
-`else
- assign \$currQ = Q;
generate case (|IS_C_INVERTED)
- 1'b0: always @(posedge C) Q <= \$nextQ ;
- 1'b1: always @(negedge C) Q <= \$nextQ ;
+ 1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+ 1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate
-`endif
endmodule
(* abc9_box_id=1002, lib_whitebox, abc9_flop *)
);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
- wire \$currQ ;
- reg \$nextQ ;
- always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ;
-`ifdef _ABC9
- // `abc9' requires that complex flops be split into a combinatorial
- // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
- // In order to achieve clock-enable behaviour, the current value
- // of the sequential output is required which Yosys will
- // connect to the special `$currQ' wire.
-
- // Special signal indicating clock domain
- // (used to partition the module so that `abc9' only performs
- // sequential synthesis (reachability analysis) correctly on
- // one domain at a time)
- wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
- // Special signal indicating control domain
- // (which, combined with this spell type, encodes to `abc9'
- // which flops may be merged together)
- wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
- always @* Q = \$nextQ ;
-`else
- assign \$currQ = Q;
- always @(negedge C) Q <= \$nextQ ;
-`endif
+ always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
endmodule
(* abc9_box_id=1003, lib_whitebox, abc9_flop *)
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
initial Q <= INIT;
- wire \$currQ ;
- reg \$nextQ ;
- always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
-`ifdef _ABC9
- // `abc9' requires that complex flops be split into a combinatorial
- // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
- // In order to achieve clock-enable behaviour, the current value
- // of the sequential output is required which Yosys will
- // connect to the special `$currQ' wire.
- // Since this is an async flop, async behaviour is also dealt with
- // using the $_ABC9_ASYNC box by abc9_map.v
-
- // Special signal indicating clock domain
- // (used to partition the module so that `abc9' only performs
- // sequential synthesis (reachability analysis) correctly on
- // one domain at a time)
- wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
- // Special signal indicating control domain
- // (which, combined with this spell type, encodes to `abc9'
- // which flops may be merged together)
- wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
- always @* Q = \$nextQ ;
-`else
- assign \$currQ = Q;
generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
- 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
- 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
- 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
- 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
+ 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+ 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+ 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+ 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate
-`endif
endmodule
(* abc9_box_id=1004, lib_whitebox, abc9_flop *)
);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
- wire \$currQ ;
- reg \$nextQ ;
- always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
-`ifdef _ABC9
- // `abc9' requires that complex flops be split into a combinatorial
- // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
- // In order to achieve clock-enable behaviour, the current value
- // of the sequential output is required which Yosys will
- // connect to the special `$currQ' wire.
- // Since this is an async flop, async behaviour is also dealt with
- // using the $_ABC9_ASYNC box by abc9_map.v
-
- // Special signal indicating clock domain
- // (used to partition the module so that `abc9' only performs
- // sequential synthesis (reachability analysis) correctly on
- // one domain at a time)
- wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
- // Special signal indicating control domain
- // (which, combined with this spell type, encodes to `abc9'
- // which flops may be merged together)
- wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
- always @* Q = \$nextQ ;
-`else
- assign \$currQ = Q;
- always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
-`endif
+ always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
endmodule
(* abc9_box_id=1005, lib_whitebox, abc9_flop *)
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
initial Q <= INIT;
- wire \$currQ ;
- reg \$nextQ ;
- always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
-`ifdef _ABC9
- // `abc9' requires that complex flops be split into a combinatorial
- // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
- // In order to achieve clock-enable behaviour, the current value
- // of the sequential output is required which Yosys will
- // connect to the special `$currQ' wire.
- // Since this is an async flop, async behaviour is also dealt with
- // using the $_ABC9_ASYNC box by abc9_map.v
-
- // Special signal indicating clock domain
- // (used to partition the module so that `abc9' only performs
- // sequential synthesis (reachability analysis) correctly on
- // one domain at a time)
- wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
- // Special signal indicating control domain
- // (which, combined with this spell type, encodes to `abc9'
- // which flops may be merged together)
- wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
- always @* Q = \$nextQ ;
-`else
- assign \$currQ = Q;
generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
- 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
- 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
- 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
- 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
+ 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ;
+ 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ;
+ 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ;
+ 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ;
endcase endgenerate
-`endif
endmodule
(* abc9_box_id=1006, lib_whitebox, abc9_flop *)
);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
- wire \$currQ ;
- reg \$nextQ ;
- always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
-`ifdef _ABC9
- // `abc9' requires that complex flops be split into a combinatorial
- // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
- // In order to achieve clock-enable behaviour, the current value
- // of the sequential output is required which Yosys will
- // connect to the special `$currQ' wire.
- // Since this is an async flop, async behaviour is also dealt with
- // using the $_ABC9_ASYNC box by abc9_map.v
-
- // Special signal indicating clock domain
- // (used to partition the module so that `abc9' only performs
- // sequential synthesis (reachability analysis) correctly on
- // one domain at a time)
- wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
- // Special signal indicating control domain
- // (which, combined with this spell type, encodes to `abc9'
- // which flops may be merged together)
- wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
- always @* Q = \$nextQ ;
-`else
- assign \$currQ = Q;
- always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
-`endif
+ always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
(* abc9_box_id=1007, lib_whitebox, abc9_flop *)
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_S_INVERTED = 1'b0;
initial Q <= INIT;
- wire \$currQ ;
- reg \$nextQ ;
- always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
-`ifdef _ABC9
- // `abc9' requires that complex flops be split into a combinatorial
- // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
- // In order to achieve clock-enable behaviour, the current value
- // of the sequential output is required which Yosys will
- // connect to the special `$currQ' wire.
-
- // Special signal indicating clock domain
- // (used to partition the module so that `abc9' only performs
- // sequential synthesis (reachability analysis) correctly on
- // one domain at a time)
- wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
- // Special signal indicating control domain
- // (which, combined with this spell type, encodes to `abc9'
- // which flops may be merged together)
- wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
- always @* Q = \$nextQ ;
-`else
- assign \$currQ = Q;
generate case (|IS_C_INVERTED)
- 1'b0: always @(posedge C) Q <= \$nextQ ;
- 1'b1: always @(negedge C) Q <= \$nextQ ;
+ 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+ 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate
-`endif
endmodule
(* abc9_box_id=1008, lib_whitebox, abc9_flop *)
);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
- wire \$currQ ;
- reg \$nextQ ;
- always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ;
-`ifdef _ABC9
- // `abc9' requires that complex flops be split into a combinatorial
- // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
- // In order to achieve clock-enable behaviour, the current value
- // of the sequential output is required which Yosys will
- // connect to the special `$currQ' wire.
-
- // Special signal indicating clock domain
- // (used to partition the module so that `abc9' only performs
- // sequential synthesis (reachability analysis) correctly on
- // one domain at a time)
- wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
- // Special signal indicating control domain
- // (which, combined with this spell type, encodes to `abc9'
- // which flops may be merged together)
- wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
- always @* Q = \$nextQ ;
-`else
- assign \$currQ = Q;
- always @(negedge C) Q <= \$nextQ ;
-`endif
+ always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
endmodule
module LDCE (
projects / yosys.git / commitdiff