Fill out the miscreg file and add types to miscregs.hh

--HG--
extra : convert_revision : 865432256518c4340d9f319bdd9b7d160dc656a0

diff --git a/src/arch/x86/miscregfile.cc b/src/arch/x86/miscregfile.cc
index 14ba3c7cce2bf4a73bd8ff5a795f91940113900b..9d8e94061196030b8bd548927d3219041cbce12c 100644 (file)
--- a/src/arch/x86/miscregfile.cc
+++ b/src/arch/x86/miscregfile.cc
@@ -86,6 +86,7 @@
  */
 
 #include "arch/x86/miscregfile.hh"
+#include "sim/serialize.hh"
 
 using namespace X86ISA;
 using namespace std;
@@ -105,31 +106,65 @@ void MiscRegFile::clear()
 
 MiscReg MiscRegFile::readRegNoEffect(int miscReg)
 {
-    panic("No misc registers in x86 yet!\n");
+    switch(miscReg)
+    {
+      case MISCREG_CR1:
+      case MISCREG_CR5:
+      case MISCREG_CR6:
+      case MISCREG_CR7:
+      case MISCREG_CR9:
+      case MISCREG_CR10:
+      case MISCREG_CR11:
+      case MISCREG_CR12:
+      case MISCREG_CR13:
+      case MISCREG_CR14:
+      case MISCREG_CR15:
+        panic("Tried to read invalid control register %d\n", miscReg);
+        break;
+    }
+    return regVal[miscReg];
 }
 
 MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
 {
-    panic("No misc registers in x86 yet!\n");
+    warn("No miscreg effects implemented yet!\n");
+    return readRegNoEffect(miscReg);
 }
 
 void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
 {
-    panic("No misc registers in x86 yet!\n");
+    switch(miscReg)
+    {
+      case MISCREG_CR1:
+      case MISCREG_CR5:
+      case MISCREG_CR6:
+      case MISCREG_CR7:
+      case MISCREG_CR9:
+      case MISCREG_CR10:
+      case MISCREG_CR11:
+      case MISCREG_CR12:
+      case MISCREG_CR13:
+      case MISCREG_CR14:
+      case MISCREG_CR15:
+        panic("Tried to write invalid control register %d\n", miscReg);
+        break;
+    }
+    regVal[miscReg] = val;
 }
 
 void MiscRegFile::setReg(int miscReg,
         const MiscReg &val, ThreadContext * tc)
 {
-    panic("No misc registers in x86 yet!\n");
+    warn("No miscreg effects implemented yet!\n");
+    setRegNoEffect(miscReg, val);
 }
 
 void MiscRegFile::serialize(std::ostream & os)
 {
-    panic("No misc registers in x86 yet!\n");
+    SERIALIZE_ARRAY(regVal, NumMiscRegs);
 }
 
 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
 {
-    panic("No misc registers in x86 yet!\n");
+    UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
 }

diff --git a/src/arch/x86/miscregfile.hh b/src/arch/x86/miscregfile.hh
index 10acb97a4bcc375f2b1163ca422e82a181fe37bc..e095e06e9bfeeae3af7b4b2311bdd9bdb34a9191 100644 (file)
--- a/src/arch/x86/miscregfile.hh
+++ b/src/arch/x86/miscregfile.hh
@@ -89,6 +89,7 @@
 #define __ARCH_X86_MISCREGFILE_HH__
 
 #include "arch/x86/faults.hh"
+#include "arch/x86/miscregs.hh"
 #include "arch/x86/types.hh"
 
 #include <string>
@@ -100,11 +101,14 @@ namespace X86ISA
     std::string getMiscRegName(RegIndex);
 
     //These will have to be updated in the future.
-    const int NumMiscArchRegs = 0;
-    const int NumMiscRegs = 0;
+    const int NumMiscArchRegs = NUM_MISCREGS;
+    const int NumMiscRegs = NUM_MISCREGS;
 
     class MiscRegFile
     {
+      protected:
+        MiscReg regVal[NumMiscRegs];
+
       public:
         void clear();
 

diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh
index 57653cd8ad1499bff4881a76afa7b665a58f1057..39425fc9d371734774fbea80e408dde915afe22c 100644 (file)
--- a/src/arch/x86/miscregs.hh
+++ b/src/arch/x86/miscregs.hh
@@ -73,6 +73,101 @@ namespace X86ISA
         OFBit = 1 << 11
     };
 
+    enum MiscRegIndex
+    {
+        // Control registers
+        // Most of these are invalid.
+        MISCREG_CR0,
+        MISCREG_CR1,
+        MISCREG_CR2,
+        MISCREG_CR3,
+        MISCREG_CR4,
+        MISCREG_CR5,
+        MISCREG_CR6,
+        MISCREG_CR7,
+        MISCREG_CR8,
+        MISCREG_CR9,
+        MISCREG_CR10,
+        MISCREG_CR11,
+        MISCREG_CR12,
+        MISCREG_CR13,
+        MISCREG_CR14,
+        MISCREG_CR15,
+
+        // Debug registers
+        MISCREG_DR0,
+        MISCREG_DR1,
+        MISCREG_DR2,
+        MISCREG_DR3,
+        MISCREG_DR4,
+        MISCREG_DR5,
+        MISCREG_DR6,
+        MISCREG_DR7,
+
+        // Flags register
+        MISCREG_RFLAGS,
+
+        // Segment selectors
+        MISCREG_ES,
+        MISCREG_CS,
+        MISCREG_SS,
+        MISCREG_DS,
+        MISCREG_FS,
+        MISCREG_GS,
+
+        // Hidden segment base field
+        MISCREG_ES_BASE,
+        MISCREG_CS_BASE,
+        MISCREG_SS_BASE,
+        MISCREG_DS_BASE,
+        MISCREG_FS_BASE,
+        MISCREG_GS_BASE,
+
+        // Hidden segment limit field
+        MISCREG_ES_LIMIT,
+        MISCREG_CS_LIMIT,
+        MISCREG_SS_LIMIT,
+        MISCREG_DS_LIMIT,
+        MISCREG_FS_LIMIT,
+        MISCREG_GS_LIMIT,
+
+        // Hidden segment limit attributes
+        MISCREG_ES_ATTR,
+        MISCREG_CS_ATTR,
+        MISCREG_SS_ATTR,
+        MISCREG_DS_ATTR,
+        MISCREG_FS_ATTR,
+        MISCREG_GS_ATTR,
+
+        // System segment selectors
+        MISCREG_LDTR,
+        MISCREG_TR,
+
+        // Hidden system segment base field
+        MISCREG_LDTR_BASE,
+        MISCREG_TR_BASE,
+        MISCREG_GDTR_BASE,
+        MISCREG_IDTR_BASE,
+
+        // Hidden system segment limit field
+        MISCREG_LDTR_LIMIT,
+        MISCREG_TR_LIMIT,
+        MISCREG_GDTR_LIMIT,
+        MISCREG_IDTR_LIMIT,
+
+        // Hidden system segment attribute field
+        MISCREG_LDTR_ATTR,
+        MISCREG_TR_ATTR,
+
+        //XXX Add "Model-Specific Registers"
+
+        NUM_MISCREGS
+    };
+
+    /**
+     * A type to describe the condition code bits of the RFLAGS register,
+     * plus two flags, EZF and ECF, which are only visible to microcode.
+     */
     BitUnion64(CCFlagBits)
         Bitfield<11> OF;
         Bitfield<7> SF;
@@ -83,6 +178,152 @@ namespace X86ISA
         Bitfield<2> PF;
         Bitfield<0> CF;
     EndBitUnion(CCFlagBits)
+
+    /**
+     * RFLAGS
+     */
+    BitUnion64(RFLAGS)
+        Bitfield<21> ID; // ID Flag
+        Bitfield<20> VIP; // Virtual Interrupt Pending
+        Bitfield<19> VIF; // Virtual Interrupt Flag
+        Bitfield<18> AC; // Alignment Check
+        Bitfield<17> VM; // Virtual-8086 Mode
+        Bitfield<16> RF; // Resume Flag
+        Bitfield<14> NT; // Nested Task
+        Bitfield<13, 12> IOPL; // I/O Privilege Level
+        Bitfield<11> OF; // Overflow Flag
+        Bitfield<10> DF; // Direction Flag
+        Bitfield<9> IF; // Interrupt Flag
+        Bitfield<8> TF; // Trap Flag
+        Bitfield<7> SF; // Sign Flag
+        Bitfield<6> ZF; // Zero Flag
+        Bitfield<4> AF; // Auxiliary Flag
+        Bitfield<2> PF; // Parity Flag
+        Bitfield<0> CF; // Carry Flag
+    EndBitUnion(RFLAGS)
+
+    /**
+     * Control registers
+     */
+    BitUnion64(CR0)
+        Bitfield<31> PG; // Paging
+        Bitfield<30> CD; // Cache Disable
+        Bitfield<29> NW; // Not Writethrough
+        Bitfield<18> AM; // Alignment Mask
+        Bitfield<16> WP; // Write Protect
+        Bitfield<5> NE; // Numeric Error
+        Bitfield<4> ET; // Extension Type
+        Bitfield<3> TS; // Task Switched
+        Bitfield<2> EM; // Emulation
+        Bitfield<1> MP; // Monitor Coprocessor
+        Bitfield<0> PE; // Protection Enabled
+    EndBitUnion(CR0)
+
+    // Page Fault Virtual Address
+    BitUnion64(CR2)
+        Bitfield<31, 0> legacy;
+    EndBitUnion(CR2)
+
+    BitUnion64(CR3)
+        Bitfield<51, 12> longPDTB; // Long Mode Page-Directory-Table
+                                   // Base Address
+        Bitfield<31, 12> PDTB; // Non-PAE Addressing Page-Directory-Table
+                               // Base Address
+        Bitfield<31, 5> PAEPDTB; // PAE Addressing Page-Directory-Table
+                                 // Base Address
+        Bitfield<4> PCD; // Page-Level Cache Disable
+        Bitfield<3> PWT; // Page-Level Writethrough
+    EndBitUnion(CR3)
+
+    BitUnion64(CR4)
+        Bitfield<10> OSXMMEXCPT; // Operating System Unmasked
+                                 // Exception Support
+        Bitfield<9> OSFXSR; // Operating System FXSave/FSRSTOR Support
+        Bitfield<8> PCE; // Performance-Monitoring Counter Enable
+        Bitfield<7> PGE; // Page-Global Enable
+        Bitfield<6> MCE; // Machine Check Enable
+        Bitfield<5> PAE; // Physical-Address Extension
+        Bitfield<4> PSE; // Page Size Extensions
+        Bitfield<3> DE; // Debugging Extensions
+        Bitfield<2> TSD; // Time Stamp Disable
+        Bitfield<1> PVI; // Protected-Mode Virtual Interrupts
+        Bitfield<0> VME; // Virtual-8086 Mode Extensions
+    EndBitUnion(CR4)
+
+    BitUnion64(CR8)
+        Bitfield<3, 0> TPR; // Task Priority Register
+    EndBitUnion(CR4)
+
+    /**
+     * Segment Selector
+     */
+    BitUnion64(SegSelector)
+        Bitfield<15, 3> SI; // Selector Index
+        Bitfield<2> TI; // Table Indicator
+        Bitfield<1, 0> RPL; // Requestor Privilege Level
+    EndBitUnion(SegSelector)
+
+    /**
+     * Segment Descriptors
+     */
+
+    BitUnion64(SegDescriptor)
+        Bitfield<63, 56> baseHigh;
+        Bitfield<39, 16> baseLow;
+        Bitfield<55> G; // Granularity
+        Bitfield<54> D; // Default Operand Size
+        Bitfield<54> B; // Default Operand Size
+        Bitfield<53> L; // Long Attribute Bit
+        Bitfield<52> AVL; // Available To Software
+        Bitfield<51, 48> limitHigh;
+        Bitfield<15, 0> limitLow;
+        Bitfield<47> P; // Present
+        Bitfield<46, 45> DPL; // Descriptor Privilege-Level
+        Bitfield<44> S; // System
+        SubBitUnion(type, 43, 40)
+            // Specifies whether this descriptor is for code or data.
+            Bitfield<43> codeOrData;
+
+            // These bit fields are for code segments
+            Bitfield<42> C; // Conforming
+            Bitfield<41> R; // Readable
+
+            // These bit fields are for data segments
+            Bitfield<42> E; // Expand-Down
+            Bitfield<41> W; // Writable
+
+            // This is used for both code and data segments.
+            Bitfield<40> A; // Accessed
+        EndSubBitUnion(type)
+    EndBitUnion(SegDescriptor)
+
+    BitUnion64(GateDescriptor)
+        Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
+        Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
+        Bitfield<31, 16> selector; // Target Code-Segment Selector
+        Bitfield<47> P; // Present
+        Bitfield<46, 45> DPL; // Descriptor Privilege-Level
+        Bitfield<43, 40> type;
+        Bitfield<36, 32> count; // Parameter Count
+    EndBitUnion(GateDescriptor)
+
+    /**
+     * Descriptor-Table Registers
+     */
+    BitUnion64(GDTR)
+    EndBitUnion(GDTR)
+
+    BitUnion64(IDTR)
+    EndBitUnion(IDTR)
+
+    BitUnion64(LDTR)
+    EndBitUnion(LDTR)
+
+    /**
+     * Task Register
+     */
+    BitUnion64(TR)
+    EndBitUnion(TR)
 };
 
 #endif // __ARCH_X86_INTREGS_HH__