radeon/llvm: Add support for v4f32 stores on R600

diff --git a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
index 65fd22f8cf5ad27cb44f99427a72c6bac17b7bc2..8ad8213eaf6b2b9afc4f1fc0f833b6f5e7413237 100644 (file)
--- a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -158,7 +158,8 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
     return;
   } else {
     switch(MI.getOpcode()) {
-    case AMDGPU::RAT_WRITE_CACHELESS_eg:
+    case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
+    case AMDGPU::RAT_WRITE_CACHELESS_128_eg:
       {
         uint64_t inst = getBinaryCodeForInstr(MI, Fixups);
         EmitByte(INSTR_NATIVE, OS);

diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 36ca24634272952bad09c17a147ca80f5e4c0c2c..6dded2fec37cca903e636ebb4135bf03301ecb1e 100644 (file)
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -124,7 +124,8 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
       return BB;
     }
 
-  case AMDGPU::RAT_WRITE_CACHELESS_eg:
+  case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
+  case AMDGPU::RAT_WRITE_CACHELESS_128_eg:
     {
       // Convert to DWORD address
       unsigned NewAddr = MRI.createVirtualRegister(

diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 0f4bbb3a04b81033916364bd8a00532244b7c2ea..ce7a17253cae9a9004cdaac5cf55da183e5f248c 100644 (file)
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -944,10 +944,8 @@ let Predicates = [isEGorCayman] in {
 
 let usesCustomInserter = 1 in {
 
-def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
-  (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, i32imm:$eop),
-  "RAT_WRITE_CACHELESS_eg $rw_gpr, $index_gpr, $eop",
-  []>
+class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name> : EG_CF_RAT <
+  0x57, 0x2, 0, (outs), ins, !strconcat(name, " $rw_gpr, $index_gpr, $eop"), []>
 {
   let RIM         = 0;
   // XXX: Have a separate instruction for non-indexed writes.
@@ -956,7 +954,7 @@ def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
   let ELEM_SIZE   = 0;
 
   let ARRAY_SIZE  = 0;
-  let COMP_MASK   = 1;
+  let COMP_MASK   = comp_mask;
   let BURST_COUNT = 0;
   let VPM         = 0;
   let MARK        = 0;
@@ -965,16 +963,34 @@ def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
 
 } // End usesCustomInserter = 1
 
+// 32-bit store
+def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
+  (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, i32imm:$eop),
+  0x1, "RAT_WRITE_CACHELESS_32_eg"
+>;
+
 // i32 global_store
 def : Pat <
   (global_store (i32 R600_TReg32_X:$val), R600_TReg32_X:$ptr),
-  (RAT_WRITE_CACHELESS_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr, 0)
+  (RAT_WRITE_CACHELESS_32_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr, 0)
 >;
 
 // Floating point global_store
 def : Pat <
   (global_store (f32 R600_TReg32_X:$val), R600_TReg32_X:$ptr),
-  (RAT_WRITE_CACHELESS_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr, 0)
+  (RAT_WRITE_CACHELESS_32_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr, 0)
+>;
+
+//128-bit store
+def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
+  (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, i32imm:$eop),
+  0xf, "RAT_WRITE_CACHELESS_128"
+>;
+
+// v4f32 global store
+def : Pat <
+  (global_store (v4f32 R600_Reg128:$val), R600_TReg32_X:$ptr),
+  (RAT_WRITE_CACHELESS_128_eg R600_Reg128:$val, R600_TReg32_X:$ptr, 0)
 >;
 
 class VTX_READ_eg <bits<8> buffer_id, dag outs, list<dag> pattern>