add sv column

diff --git a/simple_v_extension/opcodes.mdwn b/simple_v_extension/opcodes.mdwn
index 0af0ecf0556864d8e4eeb98a28d6c5a93f193b36..7a9e57072886bad5ec36aee8efd4b3aea53f5134 100644 (file)
--- a/simple_v_extension/opcodes.mdwn
+++ b/simple_v_extension/opcodes.mdwn
@@ -1,8 +1,8 @@
 
 # RV32I    "RV32I Base Integer Instruction Set"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |lui      | rd imm20        | u     | rv32i rv64i rv128i | -  |
 |auipc    | rd oimm20       | u+o  | rv32i rv64i rv128i | -  |
 |jal      | rd jimm20       | uj   | rv32i rv64i rv128i | -  |
@@ -45,8 +45,8 @@
 
 # RV64I    "RV64I Base Integer Instruction Set (in addition to RV32I)"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |lwu      | rd rs1 oimm12   |  i+l        | rv64i rv128i |   |
 |ld       | rd rs1 oimm12   |  i+l        | rv64i rv128i |   |
 |sd       | rs1 rs2 simm12  |  s          | rv64i rv128i |   |
@@ -65,8 +65,8 @@
 
 # RV128I   "RV128I Base Integer Instruction Set (in addition to RV64I)"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |ldu      | rd rs1 oimm12  |   i+l              | rv128i |   |
 |lq       | rd rs1 oimm12  |   i+l              | rv128i |   |
 |sq       | rs1 rs2 simm12 |   s                | rv128i |   |
@@ -85,8 +85,8 @@
 
 # RV32M    "RV32M Standard Extension for Integer Multiply and Divide"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |mul      | rd rs1 rs2   |     r    | rv32m rv64m rv128m |   |
 |mulh     | rd rs1 rs2   |     r    | rv32m rv64m rv128m |   |
 |mulhsu   | rd rs1 rs2   |     r    | rv32m rv64m rv128m |   |
@@ -98,8 +98,8 @@
 
 # RV64M    "RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |mulw     | rd rs1 rs2   |     r          | rv64m rv128m |   |
 |divw     | rd rs1 rs2   |     r          | rv64m rv128m |   |
 |divuw    | rd rs1 rs2   |     r          | rv64m rv128m |   |
@@ -108,8 +108,8 @@
 
 # RV128M   "RV128M Standard Extension for Integer Multiply and Divide (in addition to RV64M)"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |muld     | rd rs1 rs2   |     r                | rv128m |   |
 |divd     | rd rs1 rs2   |     r                | rv128m |   |
 |divud    | rd rs1 rs2   |     r                | rv128m |   |
@@ -118,8 +118,8 @@
 
 # RV32A    "RV32A Standard Extension for Atomic Instructions"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |lr.w     | rd rs1          | r·l | rv32a rv64a rv128a |   |
 |sc.w     | rd rs1 rs2      | r·a | rv32a rv64a rv128a |   |
 |amoswap.w| rd rs1 rs2      | r·a | rv32a rv64a rv128a |   |
@@ -134,8 +134,8 @@
 
 # RV64A    "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |lr.d     | rd rs1          | r·l      | rv64a rv128a |   |
 |sc.d     | rd rs1 rs2      | r·a      | rv64a rv128a |   |
 |amoswap.d| rd rs1 rs2      | r·a      | rv64a rv128a |   |
@@ -150,8 +150,8 @@
 
 # RV128A   "RV128A Standard Extension for Atomic Instructions (in addition to RV64A)"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |lr.q     | rd rs1          | r·l | rv128a |   |
 |sc.q     | rd rs1 rs2      | r·a | rv128a |   |
 |amoswap.q| rd rs1 rs2      | r·a | rv128a |   |
@@ -166,8 +166,8 @@
 
 # RV32S    "RV32S Standard Extension for Supervisor-level Instructions"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |ecall     |                         | none    | rv32s rv64s rv128s |   |
 |ebreak    |                         | none    | rv32s rv64s rv128s |   |
 |uret      |                         | none    | rv32s rv64s rv128s |   |
@@ -187,7 +187,7 @@
 
 # RV32F    "RV32F Standard Extension for Single-Precision Floating-Point"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
 | -------- | -------- | ------- | ------- | |
 |flw      | frd rs1           oimm12      | i+lf  | rv32f rv64f rv128f |   |
 |fsw      | rs1 frs2          simm12      | s+f   | rv32f rv64f rv128f |   |
@@ -218,8 +218,8 @@
 
 # RV64F    "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |fcvt.l.s | rd frs1  rm  |     r·m+rf      | rv64f rv128f |   |
 |fcvt.lu.s| rd frs1  rm  |     r·m+rf      | rv64f rv128f |   |
 |fcvt.s.l | frd rs1  rm  |     r·m+fr      | rv64f rv128f |   |
@@ -227,8 +227,8 @@
 
 # RV32D    "RV32D Standard Extension for Double-Precision Floating-Point"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |fld      | frd rs1   oimm12      | i+lf  | rv32d rv64d rv128d |   |
 |fsd      | rs1 frs2  simm12      | s+f   | rv32d rv64d rv128d |   |
 |fmadd.d  | frd frs1 frs2 frs3 rm | r4·m  | rv32d rv64d rv128d |   |
@@ -258,8 +258,8 @@
 
 # RV64D    "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32D)"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |fcvt.l.d | rd frs1  rm      | r·m+rf      | rv64d rv128d |   |
 |fcvt.lu.d| rd frs1  rm      | r·m+rf      | rv64d rv128d |   |
 |fmv.x.d  | rd frs1          | r+rf        | rv64d rv128d |   |
@@ -269,8 +269,8 @@
 
 # RV32Q    "RV32Q Standard Extension for Quad-Precision Floating-Point"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |flq      | frd rs1       oimm12  | i+lf   | rv32q rv64q rv128q |   |
 |fsq      | rs1 frs2      simm12  | s+f    | rv32q rv64q rv128q |   |
 |fmadd.q  | frd frs1 frs2 frs3 rm | r4·m   | rv32q rv64q rv128q |   |
@@ -302,8 +302,8 @@
 
 # RV64Q    "RV64Q Standard Extension for Quad-Precision Floating-Point (in addition to RV32Q)"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |fcvt.l.q | rd frs1  rm       | r·m+rf        | rv64q rv128q |   |
 |fcvt.lu.q| rd frs1  rm       | r·m+rf        | rv64q rv128q |   |
 |fcvt.q.l | frd rs1  rm       | r·m+fr        | rv64q rv128q |   |
@@ -311,15 +311,15 @@
 
 # RV128Q   "RV128Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV64Q)"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |fmv.x.q  | rd frs1  | r+rf          | rv64q rv128q |   |
 |fmv.q.x  | frd rs1  | r+fr          | rv64q rv128q |   |
 
 # RV32C    "RV32C Standard Extension for Compressed Instructions"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |c.addi4spn|crdq       cimm4spn  | ciw·4spn  | rv32c rv64c |   |
 |c.fld    | cfrdq crs1q   cimmd  | cl·ld+f   | rv32c rv64c |   |
 |c.lw     | crdq  crs1q   cimmw  | cl·lw     | rv32c rv64c |   |
@@ -360,8 +360,8 @@
 
 # RV64C    "RV64C Standard Extension for Compressed Instructions (in addition to RV32C)"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |c.ld     | crdq  crs1q   cimmd  | cl·ld           | rv64c |   |
 |c.sd     | crs1q crs2q   cimmd  | cs·sd           | rv64c |   |
 |c.addiw  | crs1rd        cimmi  | ci              | rv64c |   |
@@ -373,8 +373,8 @@
 
 # RV128C   "RV128C Standard Extension for Compressed Instructions (in addition to RV64C)"
 
-| (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | ------- | ------- |
+| (23..18) | (17..12) | (11..6) | (5...0) |  |
+| -------- | -------- | ------- | ------- |  |
 |c.lq     | crdq crs1q    cimmq  | cl·lq           | rv128c |   |
 |c.sq     | crs1q crs2q   cimmq  | cs·sq           | rv128c |   |
 |c.lqsp   | crd        cimmlqsp  | ci·lqsp         | rv128c |   |