def simulation(lst,RS,RA,RB):
- #lst = ["and. 3, 2, 4"]
initial_regs = [0] * 32
initial_regs[0] = RS
initial_regs[1] = RA
print(sim.gpr)
print("gpr 0 is : ")
print(hex(sim.gpr[0].value))
- #assert(sim.gpr(3) == SelectableInt(0x6ce404674f1, 64))
- #assert
return sim.gpr(0).value
# this function is extracted from bigint_cases.py (should be in a library)
t0 = self.le_bytes_to_num(m[0:8])
t1 = self.le_bytes_to_num(m[8:16])
- h0 += simulation(["and. 0, 1, 2"], h0, t0, 0xfffffffffff)
+ #h0 += simulation(["and. 0, 1, 2"], h0, t0, 0xfffffffffff)
+ # h0 = h0 + t0 & 0xfff...
+ novar = 0xdeadbeef
+ h0_sim = simulation(["and. 10, 1, 2","add 0, 0, 10"], h0, t0, 0xfffffffffff)
+ t0_temp = simulation(["srd 0, 1, 2"], novar, t0, 44)
+ t1_temp = simulation(["sld 0, 1, 2"], novar, t1, 20)
+ h1_sim = simulation(["and. 10, 1, 2","add 0, 0, 10"],
+ h1,
+ simulation(["or. 0, 1, 2"], novar, t0_temp, t1_temp),
+ 0xfffffffffff)
+ t1_temp = simulation(["srd 0, 1, 2"], novar, t1, 24)
+ t1_temp = simulation(["and. 0, 1, 2"], novar, t1_temp, 0x3ffffffffff)
+ t1_temp = simulation(["or. 0, 1, 2"], novar, t1_temp, hibit )
+ h2_sim = simulation(["add 0, 1, 2"], novar, h2, t1_temp)
+
+ h0 += t0 & 0xfffffffffff;
h1 += (((t0 >> 44) | (t1 << 20)) & 0xfffffffffff);
h2 += (((t1 >> 24) ) & 0x3ffffffffff) | hibit;
+ assert (h0 == h0_sim), "h0 and h0_sim are unequal!"
+ assert (h1 == h1_sim), "h1 and h1_sim are uneqaul!"
+ assert (h2 == h2_sim), "h2 and h2_sim are unequal!"
+
print(" loop h+t %x %x %x" % (h0, h1, h2))
#/* h *= r */