Fix typo, REP_S was refering to REP_E register.

Add test.

diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog
index fb753282fa150b9b01d41860ae9a4d3b31e34319..347585089f9ff46802e2a2dab9910bfb99b451d2 100644 (file)
--- a/sim/d10v/ChangeLog
+++ b/sim/d10v/ChangeLog
@@ -1,3 +1,7 @@
+Tue Dec  9 10:28:31 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * d10v_sim.h (RPT_S): Index cregs with RPT_S_CR not RPT_E_CR.
+
 Mon Dec  8 12:58:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
        * simops.c (OP_5F00): From Martin Hunt <hunt@cygnus.com>. Change

diff --git a/sim/d10v/d10v_sim.h b/sim/d10v/d10v_sim.h
index b05a60a47020ea33326a27a25957ca4c5aca311e..59787f15e63e23b726d1d696206bfa0b6b22810f 100644 (file)
--- a/sim/d10v/d10v_sim.h
+++ b/sim/d10v/d10v_sim.h
@@ -146,7 +146,7 @@ enum
 #define BPSW   (0 + State.cregs[PSW_CR])
 #define BPC    (State.cregs[BPC_CR])
 #define RPT_C  (State.cregs[RPT_C_CR])
-#define RPT_S  (State.cregs[RPT_E_CR])
+#define RPT_S  (State.cregs[RPT_S_CR])
 #define RPT_E  (State.cregs[RPT_E_CR])
 #define MOD_S  (0 + State.cregs[MOD_S_CR])
 #define MOD_E  (0 + State.cregs[MOD_E_CR])

diff --git a/sim/testsuite/d10v-elf/ChangeLog b/sim/testsuite/d10v-elf/ChangeLog
index c76a7b2398cf34d76b3730906a7a6c162c3fbd9f..874b6f520da79a7e035f26909d6d990e7732d7c7 100644 (file)
--- a/sim/testsuite/d10v-elf/ChangeLog
+++ b/sim/testsuite/d10v-elf/ChangeLog
@@ -1,3 +1,7 @@
+Tue Dec  9 10:41:44 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * t-rep.s: Check rep repeats correct number of times.
+
 Fri Dec  5 10:11:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
        * t-mvtc.s: Check for stuck-zero in MOD_E, MOD_S.