ARM: Fill out the printReg function.

diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index aa60b57be0b04eb73863ff593f3b1f12169ab79d..1a7853f2c60165f77ee2e7103337d670196ca6ee 100644 (file)
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -219,10 +219,29 @@ void
 ArmStaticInst::printReg(std::ostream &os, int reg) const
 {
     if (reg < FP_Base_DepTag) {
-        ccprintf(os, "r%d", reg);
-    }
-    else {
+        switch (reg) {
+          case PCReg:
+            ccprintf(os, "pc");
+            break;
+          case StackPointerReg:
+            ccprintf(os, "sp");
+            break;
+          case FramePointerReg:
+            ccprintf(os, "fp");
+            break;
+          case ReturnAddressReg:
+            ccprintf(os, "lr");
+            break;
+          default:
+            ccprintf(os, "r%d", reg);
+            break;
+        }
+    } else if (reg < Ctrl_Base_DepTag) {
         ccprintf(os, "f%d", reg - FP_Base_DepTag);
+    } else {
+        reg -= Ctrl_Base_DepTag;
+        assert(reg < NUM_MISCREGS);
+        ccprintf(os, "%s", ArmISA::miscRegName[reg]);
     }
 }
 

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index d939fabcf75cf93b263cc6a23f11e9c3990c2794..42065b0fdb839967807e1106271fd216094f13ae 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -55,12 +55,20 @@ namespace ArmISA
 
     enum MiscRegIndex {
         MISCREG_CPSR = 0,
+       MISCREG_SPSR,
         MISCREG_SPSR_FIQ,
         MISCREG_SPSR_IRQ,
         MISCREG_SPSR_SVC,
         MISCREG_SPSR_UND,
         MISCREG_SPSR_ABT,
-        MISCREG_FPSR
+        MISCREG_FPSR,
+       NUM_MISCREGS
+    };
+
+    const char * const miscRegName[NUM_MISCREGS] = {
+       "cpsr",
+       "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und", "spsr_abt",
+       "fpsr"
     };
 
     BitUnion32(CPSR)