freedreno/ir3: decouple regset from gpu gen

Allow different regset's to coexist, so we can make mergedregs vs split
reg file a variant property.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5458>

diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h
index d3e4a988dd92d5af342c649baa8a732ac0d77942..bdfce559aab5c89efce057cd51bb5b7a12b1e169 100644 (file)
--- a/src/freedreno/ir3/ir3.h
+++ b/src/freedreno/ir3/ir3.h
@@ -1317,7 +1317,7 @@ bool ir3_postsched(struct ir3 *ir);
 bool ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so);
 
 /* register assignment: */
-struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler);
+struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler, bool mergedregs);
 int ir3_ra(struct ir3_shader_variant *v, struct ir3_instruction **precolor, unsigned nprecolor);
 
 /* legalize: */

diff --git a/src/freedreno/ir3/ir3_compiler.c b/src/freedreno/ir3/ir3_compiler.c
index 76404fd7a52af583be66d261b475297c17e05c1a..7e74f9ba6da24b0bd6cce72b0142a5040a4d2aca 100644 (file)
--- a/src/freedreno/ir3/ir3_compiler.c
+++ b/src/freedreno/ir3/ir3_compiler.c
@@ -60,9 +60,10 @@ struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id
 
        compiler->dev = dev;
        compiler->gpu_id = gpu_id;
-       compiler->set = ir3_ra_alloc_reg_set(compiler);
+       compiler->set = ir3_ra_alloc_reg_set(compiler, false);
 
        if (compiler->gpu_id >= 600) {
+               compiler->mergedregs_set = ir3_ra_alloc_reg_set(compiler, true);
                compiler->samgq_workaround = true;
        }
 

diff --git a/src/freedreno/ir3/ir3_compiler.h b/src/freedreno/ir3/ir3_compiler.h
index a5af717471e50593c529c33f18b0bbc8b0d9844a..b777edf6311d90916ce7b9671c4a3209ece91211 100644 (file)
--- a/src/freedreno/ir3/ir3_compiler.h
+++ b/src/freedreno/ir3/ir3_compiler.h
@@ -35,6 +35,7 @@ struct ir3_compiler {
        struct fd_device *dev;
        uint32_t gpu_id;
        struct ir3_ra_reg_set *set;
+       struct ir3_ra_reg_set *mergedregs_set;
        uint32_t shader_count;
 
        /*

diff --git a/src/freedreno/ir3/ir3_ra.c b/src/freedreno/ir3/ir3_ra.c
index c9a1b679116ccb85b66c5e75c066850610ba6939..7812a5b70266cf18eba4b091690e79b313ceb7d2 100644 (file)
--- a/src/freedreno/ir3/ir3_ra.c
+++ b/src/freedreno/ir3/ir3_ra.c
@@ -1488,7 +1488,8 @@ ir3_ra_pass(struct ir3_shader_variant *v, struct ir3_instruction **precolor,
        struct ir3_ra_ctx ctx = {
                        .v = v,
                        .ir = v->ir,
-                       .set = v->ir->compiler->set,
+                       .set = (v->ir->compiler->gpu_id >= 600) ?
+                               v->ir->compiler->mergedregs_set : v->ir->compiler->set,
                        .scalar_pass = scalar_pass,
        };
        int ret;

diff --git a/src/freedreno/ir3/ir3_ra_regset.c b/src/freedreno/ir3/ir3_ra_regset.c
index 48fd9f106e8d45727ab971470b55a7e442a3211f..c9e6c8e21cbb52c1f98097723414ee460aedf727 100644 (file)
--- a/src/freedreno/ir3/ir3_ra_regset.c
+++ b/src/freedreno/ir3/ir3_ra_regset.c
@@ -105,7 +105,7 @@ setup_conflicts(struct ir3_ra_reg_set *set)
  * really just four scalar registers.  Don't let that confuse you.)
  */
 struct ir3_ra_reg_set *
-ir3_ra_alloc_reg_set(struct ir3_compiler *compiler)
+ir3_ra_alloc_reg_set(struct ir3_compiler *compiler, bool mergedregs)
 {
        struct ir3_ra_reg_set *set = rzalloc(compiler, struct ir3_ra_reg_set);
        unsigned ra_reg_count, reg, base;
@@ -195,7 +195,7 @@ ir3_ra_alloc_reg_set(struct ir3_compiler *compiler)
         * And finally setup conflicts.  Starting a6xx, half precision regs
         * conflict w/ full precision regs (when using MERGEDREGS):
         */
-       if (compiler->gpu_id >= 600) {
+       if (mergedregs) {
                for (unsigned i = 0; i < CLASS_REGS(0) / 2; i++) {
                        unsigned freg  = set->gpr_to_ra_reg[0][i];
                        unsigned hreg0 = set->gpr_to_ra_reg[0 + HALF_OFFSET][(i * 2) + 0];