Fix #1496.

diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc
index 29700c37b5435b191846a8695b91260368121f55..9f3bb525bdd17885330fdc74dc0dc2a741b54617 100644 (file)
--- a/passes/techmap/extract_fa.cc
+++ b/passes/techmap/extract_fa.cc
@@ -262,10 +262,14 @@ struct ExtractFaWorker
                        pool<SigBit> new_leaves = leaves;
 
                        new_leaves.erase(bit);
-                       if (cell->hasPort(ID::A)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::A))));
-                       if (cell->hasPort(ID::B)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::B))));
-                       if (cell->hasPort(ID(C))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(C)))));
-                       if (cell->hasPort(ID(D))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(D)))));
+                       for (auto port : {ID::A, ID::B, ID(C), ID(D)}) {
+                               if (!cell->hasPort(port))
+                                       continue;
+                               auto bit = sigmap(SigBit(cell->getPort(port)));
+                               if (!bit.wire)
+                                       continue;
+                               new_leaves.insert(bit);
+                       }
 
                        if (GetSize(new_leaves) > maxbreadth)
                                continue;

diff --git a/tests/various/bug1496.ys b/tests/various/bug1496.ys
new file mode 100644 (file)
index 0000000..d050161
--- /dev/null
+++ b/tests/various/bug1496.ys
@@ -0,0 +1,13 @@
+read_ilang << EOF
+module \top
+  wire input 1 \A
+  wire output 2 \Y
+  cell $_AND_ \sub
+    connect \A \A
+    connect \B 1'0
+    connect \Y \Y
+  end
+end
+EOF
+
+extract_fa