altera_quartus: fix clock domain name

diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py
index f1d366dfa896ac0e76b2f53408f78a06d18073c7..4fc7855092ffe7636d7156e9529c22ecf8d191e4 100644 (file)
--- a/mibuild/altera_quartus.py
+++ b/mibuild/altera_quartus.py
@@ -14,7 +14,7 @@ def _add_period_constraint(platform, clk, period):
 class CRG_SE(SimpleCRG):
        def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
                SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert)
-               _add_period_constraint(platform, self.cd.clk, period)
+               _add_period_constraint(platform, self.cd_sys.clk, period)
 
 def _format_constraint(c):
        if isinstance(c, Pins):