-luxc1 fix

-noop templates
-trap disassembly

src/arch/mips/isa/decoder.isa:
    luxc1 uses doubleword, not single
src/arch/mips/isa/formats/int.isa:
    use new nop decode template
src/arch/mips/isa/formats/mem.isa:
    Noop templates
src/arch/mips/isa/formats/noop.isa:
    redo noop templates
src/arch/mips/isa/formats/trap.isa:
    fix for trap disassembly

--HG--
extra : convert_revision : 56f13e88abdcbd03ab828cff5d775c993157ae96

diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 14aa0cc77cbb6fcf57522417832feaf4a33bcda0..8b9d8eeb1bf2469e8a38f86f07ed31f89f57c948 100644 (file)
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -859,7 +859,7 @@ decode OPCODE_HI default Unknown::unknown() {
                 format LoadIndexedMemory {
                     0x0: lwxc1({{ Fd.uw = Mem.uw;}});
                     0x1: ldxc1({{ Fd.ud = Mem.ud;}});
-                    0x5: luxc1({{ Fd.uw = Mem.ud;}},
+                    0x5: luxc1({{ Fd.ud = Mem.ud;}},
                                {{ EA = (Rs + Rt) & ~7; }});
                 }
             }

diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index 7b5affb5cd00e607cec81c914533e25d5f57e1b0..8ac50b009757e7919409fe107afe76c730a8936f 100644 (file)
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -228,7 +228,7 @@ def format IntOp(code, *opt_flags) {{
     iop = InstObjParams(name, Name, 'IntOp', CodeBlock(code), opt_flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
-    decode_block = OperateNopCheckDecode.subst(iop)
+    decode_block = RegNopCheckDecode.subst(iop)
     exec_output = BasicExecute.subst(iop)
 }};
 
@@ -236,7 +236,7 @@ def format IntImmOp(code, *opt_flags) {{
     iop = InstObjParams(name, Name, 'IntImmOp', CodeBlock(code), opt_flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
-    decode_block = OperateNopCheckDecode.subst(iop)
+    decode_block = ImmNopCheckDecode.subst(iop)
     exec_output = BasicExecute.subst(iop)
 }};
 
@@ -252,7 +252,7 @@ def format HiLoOp(code, *opt_flags) {{
     iop = InstObjParams(name, Name, 'HiLoOp', CodeBlock(code), opt_flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
-    decode_block = OperateNopCheckDecode.subst(iop)
+    decode_block = BasicDecode.subst(iop)
     exec_output = HiLoExecute.subst(iop)
 }};
 
@@ -260,7 +260,7 @@ def format HiLoMiscOp(code, *opt_flags) {{
     iop = InstObjParams(name, Name, 'HiLoMiscOp', CodeBlock(code), opt_flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
-    decode_block = OperateNopCheckDecode.subst(iop)
+    decode_block = BasicDecode.subst(iop)
     exec_output = HiLoExecute.subst(iop)
 }};
 

diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index cf6d3de74704a9a00ff7d3c2f3f57b058c099366..5a8930a0850b7e43fa0d8b41e5a82185561a26f1 100644 (file)
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -499,23 +499,11 @@ def template MiscCompleteAcc {{
     }
 }};
 
-// load instructions use Rt as dest, so check for
-// Rt == 0 to detect nops
-def template LoadNopCheckDecode {{
- {
-     MipsStaticInst *i = new %(class_name)s(machInst);
-     if (RT == 0) {
-         i = makeNop(i);
-     }
-     return i;
- }
-}};
-
 def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
                      mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
-                      decode_template = LoadNopCheckDecode,
+                      decode_template = ImmNopCheckDecode,
                       exec_template_base = 'Load')
 }};
 
@@ -530,7 +518,7 @@ def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
                      mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
-                      decode_template = LoadNopCheckDecode,
+                      decode_template = ImmNopCheckDecode,
                       exec_template_base = 'Load')
 }};
 
@@ -554,7 +542,7 @@ def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3;
 
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
-                      decode_template = LoadNopCheckDecode,
+                      decode_template = ImmNopCheckDecode,
                       exec_template_base = 'Load')
 }};
 
@@ -571,7 +559,6 @@ def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3;
 
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
-                      decode_template = LoadNopCheckDecode,
                       exec_template_base = 'Store')
 }};
 

diff --git a/src/arch/mips/isa/formats/noop.isa b/src/arch/mips/isa/formats/noop.isa
index 4fd8235e4b8db65d2d7b075517e690478113fb84..430c32f82ec252f242f84ce31f77b9fc73fd1ec8 100644 (file)
--- a/src/arch/mips/isa/formats/noop.isa
+++ b/src/arch/mips/isa/formats/noop.isa
@@ -1,33 +1,5 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
-
 ////////////////////////////////////////////////////////////////////
 //
 // Nop
@@ -73,7 +45,8 @@ output decoder {{
     MipsStaticInst *
     makeNop(MipsStaticInst *inst)
     {
-        MipsStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
+        std::string nop_str = "(" + inst->disassemble(0) + ")";
+        MipsStaticInst *nop = new Nop(nop_str, inst->machInst);
         delete inst;
         return nop;
     }
@@ -87,16 +60,36 @@ output exec {{
     }
 }};
 
-// integer & FP operate instructions use RT as dest, so check for
-// RT == 0 to detect nops
-def template OperateNopCheckDecode {{
+// Int & FP operate instructions use RD as dest, so check for
+// RD == 0 to detect nops
+def template RegNopCheckDecode {{
  {
      MipsStaticInst *i = new %(class_name)s(machInst);
+     //if (RD == 0) {
+         //i = makeNop(i);
+         //}
+     return i;
+ }
+}};
 
+def template OperateNopCheckDecode {{
+ {
+     MipsStaticInst *i = new %(class_name)s(machInst);
      //if (RD == 0) {
-     //  i = makeNop(i);
+     // i = makeNop(i);
      //}
+     return i;
+ }
+}};
 
+// IntImm & Memory  instructions use Rt as dest, so check for
+// Rt == 0 to detect nops
+def template ImmNopCheckDecode {{
+ {
+     MipsStaticInst *i = new %(class_name)s(machInst);
+     //if (RT == 0) {
+     // i = makeNop(i);
+     // }
      return i;
  }
 }};

diff --git a/src/arch/mips/isa/formats/trap.isa b/src/arch/mips/isa/formats/trap.isa
index 574b808cce52b8e3a4b416b0ce395bede79daa1b..6692e8ef87211f82de8b8c6518a313eccbf81516 100644 (file)
--- a/src/arch/mips/isa/formats/trap.isa
+++ b/src/arch/mips/isa/formats/trap.isa
@@ -70,9 +70,11 @@ def template TrapExecute {{
 }};
 
 def format Trap(code, *flags) {{
-        code = 'panic(\"'
-        code += 'Trap Exception Handler Is Currently Not Implemented.'
-        code += '\");'
+        warn_code = 'warn(\"'
+        warn_code += 'Trap Exception Handler Is Currently Not Implemented.'
+        warn_code += '\");'
+        code = warn_code + "bool " + code
+
         iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)