tests: remove write_ilang
authorEddie Hung <eddie@fpgeh.com>
Mon, 20 Apr 2020 22:42:29 +0000 (15:42 -0700)
committerEddie Hung <eddie@fpgeh.com>
Mon, 20 Apr 2020 22:42:29 +0000 (15:42 -0700)
tests/arch/ecp5/memories.ys
tests/arch/ice40/memories.ys

index e1f748e26bfcdd9c378ddb0a5eaf457e629ad731..f55bf01d2ab9a3f9e6f153a30aae5da10faea29b 100644 (file)
@@ -208,7 +208,6 @@ select -assert-count 1 t:PDPW16KD
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
-write_ilang
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:PDPW16KD # too inefficient
 select -assert-min 18 t:LUT4
@@ -274,7 +273,6 @@ select -assert-count 1 t:DP16KD
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
-write_ilang
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:DP16KD # too inefficient
 select -assert-min 9 t:LUT4
index 571edec1de8d1aa49591a3def89e71de4dae5f0a..c32f12315b7828c0ae8cfc0baccf33b5d72b0906 100644 (file)
@@ -112,7 +112,6 @@ select -assert-count 1 t:SB_RAM40_4K
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
-write_ilang
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 0 t:SB_RAM40_4K # too inefficient
 select -assert-min 1 t:SB_LUT4