surf_drm->tile_split = surf_ws->tile_split;
surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
- for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
+ for (i = 0; i <= surf_drm->last_level; i++) {
surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i], bpe);
surf_level_winsys_to_drm(&surf_drm->stencil_level[i],
&surf_ws->stencil_level[i], bpe);
surf_ws->macro_tile_index = cik_get_macro_tile_index(surf_ws);
- for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
+ for (i = 0; i <= surf_drm->last_level; i++) {
surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i],
surf_drm->bpe * surf_drm->nsamples);
surf_level_drm_to_winsys(&surf_ws->stencil_level[i],