svp64.py: allow macros as register names

This patch enables things like *fv0, where *fv0 is just a macro.
https://bugs.libre-soc.org/show_bug.cgi?id=884

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 75d22f7c0a8dc6a7ef31a1bfeb568c504e952a80..f4b03a5f276967d0570f2f97660fc3e7228b97a9 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -466,14 +466,21 @@ def decode_ffirst(encoding):
     return decode_bo(encoding)
 
 
-def decode_reg(field):
+def decode_reg(field, macros=None):
+    if macros is None:
+        macros = {}
     # decode the field number. "5.v" or "3.s" or "9"
     # and now also "*0", and "*%0".  note: *NOT* to add "*%rNNN" etc.
     # https://bugs.libre-soc.org/show_bug.cgi?id=884#c0
-    if field.startswith("*%"):
-        return int(field[2:]), "vector"  # actual register number
-    if field.startswith("*"):
-        return int(field[1:]), "vector"  # actual register number
+    if field.startswith(("*%", "*")):
+        if field.startswith("*%"):
+            field = field[2:]
+        else:
+            field = field[1:]
+        while field in macros:
+            field = macros[field]
+        return int(field), "vector"  # actual register number
+
     # try old convention (to be retired)
     field = field.split(".")
     regmode = 'scalar'  # default
@@ -718,7 +725,7 @@ class SVP64Asm:
             if ldst_imm:
                 immed, field = field[:-1].split("(")
 
-            field, regmode = decode_reg(field)
+            field, regmode = decode_reg(field, macros=macros)
             log("    ", extra_idx, rname, rtype,
                 regmode, iname, field, end=" ")